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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/8] drm/i915: implement WaForceL3Serialization on VLV and IVB
Date: Thu, 25 Oct 2012 12:15:43 -0700	[thread overview]
Message-ID: <1351192548-2992-3-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1351192548-2992-1-git-send-email-jbarnes@virtuousgeek.org>

References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a5ae0e7..d04e87f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3653,6 +3653,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_ROW_CHICKEN2,
 		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 
+	/* WaForceL3Serialization */
+	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
+		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
 	/* This is required by WaCatErrorRejectionIssue */
 	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
-- 
1.7.9.5

  parent reply	other threads:[~2012-10-25 19:15 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-25 19:15 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-25 19:15 ` Jesse Barnes [this message]
2012-10-25 19:15 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV Jesse Barnes
2012-11-01 14:48   ` Antti Koskipää
2012-11-01 14:50     ` Jesse Barnes
2012-11-01 14:52       ` Antti Koskipää
2012-10-25 19:15 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op Jesse Barnes
2012-10-26 11:13   ` Chris Wilson
2012-10-26 16:42     ` Jesse Barnes
2012-11-02 12:41       ` Chris Wilson
2012-10-25 19:15 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-25 19:15 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
2012-11-02 15:34   ` Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2012-10-18 18:07 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization on VLV and IVB Jesse Barnes
2012-10-18 15:43 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 15:43 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization on VLV and IVB Jesse Barnes

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