From: nicolas.pitre@linaro.org (Nicolas Pitre)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 05/16] ARM: bL_head: vlock-based first man election
Date: Wed, 09 Jan 2013 19:20:40 -0500 [thread overview]
Message-ID: <1357777251-13541-6-git-send-email-nicolas.pitre@linaro.org> (raw)
In-Reply-To: <1357777251-13541-1-git-send-email-nicolas.pitre@linaro.org>
From: Dave Martin <dave.martin@linaro.org>
Instead of requiring the first man to be elected in advance (which
can be suboptimal in some situations), this patch uses a per-
cluster mutex to co-ordinate selection of the first man.
This should also make it more feasible to reuse this code path for
asynchronous cluster resume (as in CPUidle scenarios).
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
---
arch/arm/common/Makefile | 2 +-
arch/arm/common/bL_head.S | 91 ++++++++++++++++++++++++++++++++++++++++-------
2 files changed, 80 insertions(+), 13 deletions(-)
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 50880c494f..894c2ddf9b 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -15,4 +15,4 @@ obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
obj-$(CONFIG_FIQ_GLUE) += fiq_glue.o fiq_glue_setup.o
obj-$(CONFIG_FIQ_DEBUGGER) += fiq_debugger.o
-obj-$(CONFIG_BIG_LITTLE) += bL_head.o bL_entry.o
+obj-$(CONFIG_BIG_LITTLE) += bL_head.o bL_entry.o vlock.o
diff --git a/arch/arm/common/bL_head.S b/arch/arm/common/bL_head.S
index f7a64ac127..e70dd432e8 100644
--- a/arch/arm/common/bL_head.S
+++ b/arch/arm/common/bL_head.S
@@ -16,6 +16,8 @@
#include <linux/linkage.h>
#include <asm/bL_entry.h>
+#include "vlock.h"
+
.if BL_SYNC_CLUSTER_CPUS
.error "cpus must be the first member of struct bL_cluster_sync_struct"
.endif
@@ -64,10 +66,11 @@ ENTRY(bL_entry_point)
* position independent way.
*/
adr r5, 3f
- ldmia r5, {r6, r7, r8}
+ ldmia r5, {r6, r7, r8, r11}
add r6, r5, r6 @ r6 = bL_entry_vectors
ldr r7, [r5, r7] @ r7 = bL_power_up_setup_phys
add r8, r5, r8 @ r8 = bL_sync
+ add r11, r5, r11 @ r11 = first_man_locks
mov r0, #BL_SYNC_CLUSTER_SIZE
mla r8, r0, r10, r8 @ r8 = bL_sync cluster base
@@ -83,11 +86,25 @@ ENTRY(bL_entry_point)
@ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
@ state, because there is at least one active CPU (this CPU).
- @ Check if the cluster has been set up yet:
+ mov r0, #.Lvlock_size
+ mla r11, r0, r10, r11 @ r11 = cluster first man lock
+ mov r0, r11
+ mov r1, r9 @ cpu
+ bl vlock_trylock
+
+ cmp r0, #0 @ failed to get the lock?
+ bne cluster_setup_wait @ wait for cluster setup if so
+
ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
- cmp r0, #CLUSTER_UP
- beq cluster_already_up
+ cmp r0, #CLUSTER_UP @ cluster already up?
+ bne cluster_setup @ if not, set up the cluster
+
+ @ Otherwise, release the first man lock and skip setup:
+ mov r0, r11
+ bl vlock_unlock
+ b cluster_setup_complete
+cluster_setup:
@ Signal that the cluster is being brought up:
mov r0, #INBOUND_COMING_UP
strb r0, [r8, #BL_SYNC_CLUSTER_INBOUND]
@@ -102,26 +119,47 @@ ENTRY(bL_entry_point)
cluster_teardown_wait:
ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
cmp r0, #CLUSTER_GOING_DOWN
- wfeeq
- beq cluster_teardown_wait
+ bne first_man_setup
+ wfe
+ b cluster_teardown_wait
+
+first_man_setup:
+ @ If the outbound gave up before teardown started, skip cluster setup:
- @ power_up_setup is responsible for setting up the cluster:
+ cmp r0, #CLUSTER_UP
+ beq cluster_setup_leave
+
+ @ power_up_setup is now responsible for setting up the cluster:
cmp r7, #0
mov r0, #1 @ second (cluster) affinity level
blxne r7 @ Call power_up_setup if defined
+ dsb
+ mov r0, #CLUSTER_UP
+ strb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
+
+cluster_setup_leave:
@ Leave the cluster setup critical section:
- dsb
mov r0, #INBOUND_NOT_COMING_UP
strb r0, [r8, #BL_SYNC_CLUSTER_INBOUND]
- mov r0, #CLUSTER_UP
- strb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
dsb
sev
-cluster_already_up:
+ mov r0, r11
+ bl vlock_unlock
+ b cluster_setup_complete
+
+ @ In the contended case, non-first men wait here for cluster setup
+ @ to complete:
+cluster_setup_wait:
+ ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
+ cmp r0, #CLUSTER_UP
+ wfene
+ bne cluster_setup_wait
+
+cluster_setup_complete:
@ If a platform-specific CPU setup hook is needed, it is
@ called from here.
@@ -150,11 +188,40 @@ bL_entry_gated:
3: .word bL_entry_vectors - .
.word bL_power_up_setup_phys - 3b
.word bL_sync - 3b
+ .word first_man_locks - 3b
ENDPROC(bL_entry_point)
.bss
- .align 5
+
+ @ Magic to size and align the first-man vlock structures
+ @ so that each does not cross a 1KB boundary.
+ @ We also must ensure that none of these shares a cacheline with
+ @ any data which might be accessed through the cache.
+
+ .equ .Log2, 0
+ .rept 11
+ .if (1 << .Log2) < VLOCK_SIZE
+ .equ .Log2, .Log2 + 1
+ .endif
+ .endr
+ .if .Log2 > 10
+ .error "vlock struct is too large for guaranteed barrierless access ordering"
+ .endif
+ .equ .Lvlock_size, 1 << .Log2
+
+ @ The presence of two .align directives here is deliberate: we must
+ @ align to whichever of the two boundaries is larger:
+ .align __CACHE_WRITEBACK_ORDER
+ .align .Log2
+first_man_locks:
+ .rept BL_NR_CLUSTERS
+ .space .Lvlock_size
+ .endr
+ .size first_man_locks, . - first_man_locks
+ .type first_man_locks, #object
+
+ .align __CACHE_WRITEBACK_ORDER
.type bL_entry_vectors, #object
ENTRY(bL_entry_vectors)
--
1.8.0
next prev parent reply other threads:[~2013-01-10 0:20 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-10 0:20 [PATCH 00/16] big.LITTLE low-level CPU and cluster power management Nicolas Pitre
2013-01-10 0:20 ` [PATCH 01/16] ARM: b.L: secondary kernel entry code Nicolas Pitre
2013-01-10 7:12 ` Stephen Boyd
2013-01-10 15:30 ` Nicolas Pitre
2013-01-10 15:34 ` Catalin Marinas
2013-01-10 16:47 ` Nicolas Pitre
2013-01-11 11:45 ` Catalin Marinas
2013-01-11 12:05 ` Lorenzo Pieralisi
2013-01-11 12:19 ` Dave Martin
2013-01-10 23:05 ` Will Deacon
2013-01-11 1:26 ` Nicolas Pitre
2013-01-11 10:55 ` Will Deacon
2013-01-11 11:35 ` Dave Martin
2013-01-11 17:16 ` Santosh Shilimkar
2013-01-11 18:10 ` Nicolas Pitre
2013-01-11 18:30 ` Santosh Shilimkar
2013-03-07 7:37 ` Pavel Machek
2013-03-07 8:57 ` Nicolas Pitre
2013-01-10 0:20 ` [PATCH 02/16] ARM: b.L: introduce the CPU/cluster power API Nicolas Pitre
2013-01-10 23:08 ` Will Deacon
2013-01-11 2:30 ` Nicolas Pitre
2013-01-11 10:58 ` Will Deacon
2013-01-11 11:29 ` Dave Martin
2013-01-11 17:26 ` Santosh Shilimkar
2013-01-11 18:33 ` Nicolas Pitre
2013-01-11 18:41 ` Santosh Shilimkar
2013-01-11 19:54 ` Nicolas Pitre
2013-01-10 0:20 ` [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup Nicolas Pitre
2013-01-10 12:01 ` Dave Martin
2013-01-10 19:04 ` Nicolas Pitre
2013-01-11 11:30 ` Dave Martin
2013-01-10 16:53 ` Catalin Marinas
2013-01-10 17:59 ` Nicolas Pitre
2013-01-10 21:50 ` Catalin Marinas
2013-01-10 22:31 ` Nicolas Pitre
2013-01-11 10:36 ` Dave Martin
2013-01-10 22:32 ` Nicolas Pitre
2013-01-10 23:13 ` Will Deacon
2013-01-11 1:50 ` Nicolas Pitre
2013-01-11 11:09 ` Dave Martin
2013-01-11 17:46 ` Santosh Shilimkar
2013-01-11 18:07 ` Dave Martin
2013-01-11 18:34 ` Santosh Shilimkar
2013-01-14 17:08 ` Dave Martin
2013-01-14 17:15 ` Catalin Marinas
2013-01-14 18:10 ` Dave Martin
2013-01-14 21:34 ` Catalin Marinas
2013-01-10 0:20 ` [PATCH 04/16] ARM: b.L: Add baremetal voting mutexes Nicolas Pitre
2013-01-10 23:18 ` Will Deacon
2013-01-11 3:15 ` Nicolas Pitre
2013-01-11 11:03 ` Will Deacon
2013-01-11 16:57 ` Dave Martin
2013-01-10 0:20 ` Nicolas Pitre [this message]
2013-01-10 0:20 ` [PATCH 06/16] ARM: b.L: generic SMP secondary bringup and hotplug support Nicolas Pitre
2013-01-11 18:02 ` Santosh Shilimkar
2013-01-14 18:05 ` Achin Gupta
2013-01-15 6:32 ` Santosh Shilimkar
2013-01-15 11:18 ` Achin Gupta
2013-01-15 11:26 ` Santosh Shilimkar
2013-01-15 18:53 ` Dave Martin
2013-01-14 16:35 ` Will Deacon
2013-01-14 16:51 ` Nicolas Pitre
2013-01-15 19:09 ` Dave Martin
2013-01-10 0:20 ` [PATCH 07/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU Nicolas Pitre
2013-01-14 16:37 ` Will Deacon
2013-01-14 16:53 ` Nicolas Pitre
2013-01-14 17:00 ` Will Deacon
2013-01-14 17:11 ` Catalin Marinas
2013-01-14 17:15 ` Nicolas Pitre
2013-01-14 17:23 ` Will Deacon
2013-01-14 18:26 ` Russell King - ARM Linux
2013-01-14 18:49 ` Nicolas Pitre
2013-01-15 18:40 ` Dave Martin
2013-01-16 16:06 ` Catalin Marinas
2013-01-10 0:20 ` [PATCH 08/16] ARM: bL_platsmp.c: make sure the GIC interface of a dying CPU is disabled Nicolas Pitre
2013-01-11 18:07 ` Santosh Shilimkar
2013-01-11 19:07 ` Nicolas Pitre
2013-01-12 6:50 ` Santosh Shilimkar
2013-01-12 16:47 ` Nicolas Pitre
2013-01-13 4:37 ` Santosh Shilimkar
2013-01-14 17:53 ` Lorenzo Pieralisi
2013-01-14 16:39 ` Will Deacon
2013-01-14 16:54 ` Nicolas Pitre
2013-01-14 17:02 ` Will Deacon
2013-01-14 17:18 ` Nicolas Pitre
2013-01-14 17:24 ` Will Deacon
2013-01-14 17:56 ` Lorenzo Pieralisi
2013-01-10 0:20 ` [PATCH 09/16] ARM: vexpress: Select the correct SMP operations at run-time Nicolas Pitre
2013-01-10 0:20 ` [PATCH 10/16] ARM: vexpress: introduce DCSCB support Nicolas Pitre
2013-01-11 18:12 ` Santosh Shilimkar
2013-01-11 19:13 ` Nicolas Pitre
2013-01-12 6:52 ` Santosh Shilimkar
2013-01-10 0:20 ` [PATCH 11/16] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation Nicolas Pitre
2013-01-10 0:20 ` [PATCH 12/16] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster Nicolas Pitre
2013-01-10 0:20 ` [PATCH 13/16] drivers: misc: add ARM CCI support Nicolas Pitre
2013-01-11 18:20 ` Santosh Shilimkar
2013-01-11 19:22 ` Nicolas Pitre
2013-01-12 6:53 ` Santosh Shilimkar
2013-01-15 18:34 ` Dave Martin
2013-01-10 0:20 ` [PATCH 14/16] ARM: TC2: ensure powerdown-time data is flushed from cache Nicolas Pitre
2013-01-10 18:50 ` Dave Martin
2013-01-10 19:13 ` Nicolas Pitre
2013-01-11 11:38 ` Dave Martin
2013-01-10 0:20 ` [PATCH 15/16] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Nicolas Pitre
2013-01-10 12:05 ` Dave Martin
2013-01-11 18:27 ` Santosh Shilimkar
2013-01-11 19:28 ` Nicolas Pitre
2013-01-12 7:21 ` Santosh Shilimkar
2013-01-14 12:25 ` Lorenzo Pieralisi
2013-01-15 6:23 ` Santosh Shilimkar
2013-01-15 18:20 ` Dave Martin
2013-01-16 6:33 ` Santosh Shilimkar
2013-01-16 10:03 ` Lorenzo Pieralisi
2013-01-16 10:12 ` Santosh Shilimkar
2013-01-10 0:20 ` [PATCH 16/16] ARM: vexpress/dcscb: probe via device tree Nicolas Pitre
2013-01-10 0:46 ` [PATCH 00/16] big.LITTLE low-level CPU and cluster power management Rob Herring
2013-01-10 5:04 ` Nicolas Pitre
2013-01-10 23:01 ` Will Deacon
[not found] ` <1357777251-13541-1-git-send-email-nicolas.pitre-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2013-01-14 9:56 ` Joseph Lo
2013-01-14 9:56 ` Joseph Lo
[not found] ` <1358157392.19304.243.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2013-01-14 14:05 ` Nicolas Pitre
2013-01-14 14:05 ` Nicolas Pitre
[not found] ` <alpine.LFD.2.02.1301140849020.6300-QuJgVwGFrdf/9pzu0YdTqQ@public.gmane.org>
2013-01-15 2:44 ` Joseph Lo
2013-01-15 2:44 ` Joseph Lo
[not found] ` <1358217848.8513.14.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2013-01-15 16:44 ` Nicolas Pitre
2013-01-15 16:44 ` Nicolas Pitre
2013-01-16 16:02 ` Catalin Marinas
2013-01-16 16:02 ` Catalin Marinas
[not found] ` <20130116160242.GB31318-5wv7dgnIgG8@public.gmane.org>
2013-01-16 21:18 ` Nicolas Pitre
2013-01-16 21:18 ` Nicolas Pitre
[not found] ` <alpine.LFD.2.02.1301161614390.6300-QuJgVwGFrdf/9pzu0YdTqQ@public.gmane.org>
2013-01-17 17:55 ` Catalin Marinas
2013-01-17 17:55 ` Catalin Marinas
2013-01-15 18:31 ` Dave Martin
2013-01-15 18:31 ` Dave Martin
2013-03-07 8:27 ` Pavel Machek
2013-03-07 9:12 ` Nicolas Pitre
2013-03-07 9:40 ` Pavel Machek
2013-03-07 9:56 ` Nicolas Pitre
2013-03-07 14:51 ` Pavel Machek
2013-03-07 15:42 ` Nicolas Pitre
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