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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 9/9] drm/i915: Don't touch VGA0/VGA1/VGA_PD on ILK+
Date: Fri, 25 Jan 2013 21:44:49 +0200	[thread overview]
Message-ID: <1359143089-14284-10-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1359143089-14284-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VGA0/VGA1/VGA_PD registers apparently haven't existed since Gen4.
Don't touch them on more recent platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_suspend.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 359ca24..75d981a 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -70,9 +70,11 @@ static void i915_save_vga(struct drm_device *dev)
 	u16 cr_index, cr_data, st01;
 
 	/* VGA state */
-	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
-	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
-	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
+	if (INTEL_INFO(dev)->gen <= 4) {
+		dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
+		dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
+		dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
+	}
 	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
 
 	/* VGA color palette registers */
@@ -136,11 +138,13 @@ static void i915_restore_vga(struct drm_device *dev)
 	/* VGA state */
 	I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
 
-	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
-	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
-	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
-	POSTING_READ(VGA_PD);
-	udelay(150);
+	if (INTEL_INFO(dev)->gen <= 4) {
+		I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
+		I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
+		I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
+		POSTING_READ(VGA_PD);
+		udelay(150);
+	}
 
 	/* MSR bits */
 	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
-- 
1.7.12.4

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      parent reply	other threads:[~2013-01-25 19:45 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-25 19:44 [PATCH 0/9] drm/915: Get rid of IS_DISPLAYREG(), continued ville.syrjala
2013-01-25 19:44 ` [PATCH v2 1/9] drm/i915: PLL registers need an offset on VLV ville.syrjala
2013-01-25 19:44 ` [PATCH 2/9] drm/i915: Always use adpa_reg ville.syrjala
2013-01-25 19:44 ` [PATCH 3/9] drm/i915: VLV doesn't have SDVO ville.syrjala
2013-01-25 19:44 ` [PATCH v2 4/9] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV ville.syrjala
2013-01-25 19:44 ` [PATCH 5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers ville.syrjala
2013-01-26 16:43   ` Daniel Vetter
2013-01-25 19:44 ` [PATCH 6/9] drm/i915: Introduce i915_vgacntrl_reg() ville.syrjala
2013-01-25 19:44 ` [PATCH 7/9] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
2013-01-25 19:44 ` [PATCH 8/9] drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too ville.syrjala
2013-01-31 10:24   ` Daniel Vetter
2013-01-25 19:44 ` ville.syrjala [this message]

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