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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: Print the pipe control page GTT address
Date: Tue, 12 Feb 2013 22:01:38 +0200	[thread overview]
Message-ID: <1360699299-22847-1-git-send-email-ville.syrjala@linux.intel.com> (raw)

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We already print the HWS addresses during init, so do the same for the
pipe control page. Reduces guesswork when looking at hex addresses
later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 00525ff..9b8b058 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -467,6 +467,9 @@ init_pipe_control(struct intel_ring_buffer *ring)
 	if (pc->cpu_page == NULL)
 		goto err_unpin;
 
+	DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
+			 ring->name, pc->gtt_offset);
+
 	pc->obj = obj;
 	ring->private = pc;
 	return 0;
-- 
1.7.12.4

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             reply	other threads:[~2013-02-12 20:01 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-12 20:01 ville.syrjala [this message]
2013-02-12 20:01 ` [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala
2013-02-13  0:53   ` Ben Widawsky
2013-02-12 20:56 ` [PATCH 1/2] drm/i915: Print the pipe control page GTT address Daniel Vetter

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