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From: ben.dooks@codethink.co.uk (Ben Dooks)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 9/9] mvebu: support running big-endian
Date: Wed, 13 Feb 2013 10:55:27 +0000	[thread overview]
Message-ID: <1360752927-29331-10-git-send-email-ben.dooks@codethink.co.uk> (raw)
In-Reply-To: <1360752927-29331-1-git-send-email-ben.dooks@codethink.co.uk>

Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-mvebu/Kconfig        |    1 +
 arch/arm/mach-mvebu/coherency_ll.S |    3 +++
 arch/arm/mach-mvebu/headsmp.S      |    2 ++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..2afa026 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_MVEBU
 	bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select CLKSRC_MMIO
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391..bc2d70d 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -20,6 +20,8 @@
 #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
 
+#include <asm/assembler.h>
+
 	.text
 /*
  * r0: Coherency fabric base register address
@@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent)
 	/* Create bit by cpu index */
 	mov	r3, #(1 << 24)
 	lsl	r1, r3, r1
+ARM_BE8(rev	r1, r1)
 
 	/* Add CPU to SMP group - Atomic */
 	add	r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ed..3b77eac 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -36,6 +36,8 @@
  */
 ENTRY(armada_xp_secondary_startup)
 
+ ARM_BE8(setend	be )			@ go BE8 if booted LE
+
 	/* Read CPU id */
 	mrc     p15, 0, r1, c0, c0, 5
 	and     r1, r1, #0xF
-- 
1.7.10.4

  parent reply	other threads:[~2013-02-13 10:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-13 10:55 [RFC v3] Better BE support for ARM Ben Dooks
2013-02-13 10:55 ` [PATCH 1/9] ARM: fix ARCH_IXP4xx usage of ARCH_SUPPORTS_BIG_ENDIAN Ben Dooks
2013-02-18 19:58   ` Krzysztof Halasa
2013-02-13 10:55 ` [PATCH 2/9] ARM: fixup_pv_table bug when CPU_ENDIAN_BE8 Ben Dooks
2013-02-19 12:04   ` Dave Martin
2013-02-13 10:55 ` [PATCH 3/9] ARM: asm: Add ARM_BE8() assembly helper Ben Dooks
2013-02-14  4:27   ` Nicolas Pitre
2013-02-19 12:07     ` Dave Martin
2013-02-13 10:55 ` [PATCH 4/9] ARM: set BE8 if LE in head code Ben Dooks
2013-02-14  4:33   ` Nicolas Pitre
2013-02-13 10:55 ` [PATCH 5/9] ARM: pl01x debug code endian fix Ben Dooks
2013-02-19 12:27   ` Dave Martin
2013-02-13 10:55 ` [PATCH 6/9] ARM: twd: data " Ben Dooks
2013-02-13 10:55 ` [PATCH 7/9] ARM: smp_scu: data endian fixes Ben Dooks
2013-02-13 10:55 ` [PATCH 8/9] highbank: enable big-endian Ben Dooks
2013-02-13 10:55 ` Ben Dooks [this message]
2013-02-15 11:39 ` [RFC v3] Better BE support for ARM Ben Dooks
2013-02-19 12:00 ` Dave Martin

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