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From: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>,
	Fabio Estevam
	<fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
	Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Subject: [PATCH 5/5] spi/mxs: Fix multiple slave bug and don't set clock for each xfer
Date: Fri, 29 Mar 2013 08:19:41 -0700	[thread overview]
Message-ID: <1364570381-17605-5-git-send-email-tpiepho@gmail.com> (raw)
In-Reply-To: <1364570381-17605-1-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Despite many warnings in the SPI documentation and code, the spi-mxs
driver sets shared chip registers in the ->setup method.  This method can
be called when transfers are in progress on other slaves controlled by the
master.  Setting registers or any other shared state will corrupt those
transfers.

So fix mxs_spi_setup() to not call mxs_spi_setup_transfer().

Now that mxs_spi_setup_transfer() won't be called with a NULL transfer,
since it's only purpose is to setup a transfer, the code can be
simplified.

mxs_spi_setup_transfer() would set the SSP SCK rate every time it was
called, which is before each transfer.  It is uncommon for the SCK rate to
change between transfers and this causes unnecessary reprogramming of the
clock registers.  Changed to only set the rate when it has changed.

This significantly speeds up short SPI messages, especially messages made
up of many transfers.  On an iMX287, using spidev with messages that
consist of 511 transfers of 4 bytes each at an SCK of 48 MHz, the
effective transfer rate more than doubles from about 290 KB/sec to 600
KB/sec.

Signed-off-by: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
Cc: Fabio Estevam <fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Cc: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 drivers/spi/spi-mxs.c |   54 ++++++++++++++++++++++++-------------------------
 1 file changed, 26 insertions(+), 28 deletions(-)

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index fc52f78..b60baab 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -66,44 +66,47 @@
 struct mxs_spi {
 	struct mxs_ssp		ssp;
 	struct completion	c;
+	unsigned int		sck;	/* Rate requested (vs actual) */
 };
 
 static int mxs_spi_setup_transfer(struct spi_device *dev,
-				struct spi_transfer *t)
+				  const struct spi_transfer *t)
 {
 	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
 	struct mxs_ssp *ssp = &spi->ssp;
-	uint8_t bits_per_word;
-	uint32_t hz = 0;
-
-	bits_per_word = dev->bits_per_word;
-	if (t && t->bits_per_word)
-		bits_per_word = t->bits_per_word;
+	const unsigned int bits_per_word = t->bits_per_word ? : dev->bits_per_word;
+	const unsigned int hz = t->speed_hz ? min(dev->max_speed_hz, t->speed_hz) :
+					      dev->max_speed_hz;
 
 	if (bits_per_word != 8) {
-		dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n",
-					__func__, bits_per_word);
+		dev_err(&dev->dev, "Unsupported bits per word of %d\n",
+			bits_per_word);
 		return -EINVAL;
 	}
 
-	hz = dev->max_speed_hz;
-	if (t && t->speed_hz)
-		hz = min(hz, t->speed_hz);
 	if (hz == 0) {
-		dev_err(&dev->dev, "Cannot continue with zero clock\n");
+		dev_err(&dev->dev, "SPI clock rate of zero not possible\n");
 		return -EINVAL;
 	}
 
-	mxs_ssp_set_clk_rate(ssp, hz);
+	if (hz != spi->sck) {
+		mxs_ssp_set_clk_rate(ssp, hz);
+		/* Save requested value, not actual value from ssp->clk_rate.
+		 * Otherwise we would set the rate again each trasfer when
+		 * actual is not quite the same as requested.  */
+		spi->sck = hz;
+		/* Perhaps we should return an error if the actual clock is
+		 * nowhere close? */
+	}
 
 	writel(BM_SSP_CTRL0_LOCK_CS,
 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+
 	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
-		     BF_SSP_CTRL1_WORD_LENGTH
-		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
-		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
-		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
-		     ssp->base + HW_SSP_CTRL1(ssp));
+	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
+	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
+	       ssp->base + HW_SSP_CTRL1(ssp));
 
 	writel(0x0, ssp->base + HW_SSP_CMD0);
 	writel(0x0, ssp->base + HW_SSP_CMD1);
@@ -113,21 +116,16 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
 
 static int mxs_spi_setup(struct spi_device *dev)
 {
-	int err = 0;
-
 	if (!dev->bits_per_word)
 		dev->bits_per_word = 8;
 
-	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
+	if (dev->bits_per_word != 8)
 		return -EINVAL;
 
-	err = mxs_spi_setup_transfer(dev, NULL);
-	if (err) {
-		dev_err(&dev->dev,
-			"Failed to setup transfer, error = %d\n", err);
-	}
+	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
+		return -EINVAL;
 
-	return err;
+	return 0;
 }
 
 static u32 mxs_spi_cs_to_reg(unsigned cs)
-- 
1.7.10.4


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WARNING: multiple messages have this Message-ID (diff)
From: tpiepho@gmail.com (Trent Piepho)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] spi/mxs: Fix multiple slave bug and don't set clock for each xfer
Date: Fri, 29 Mar 2013 08:19:41 -0700	[thread overview]
Message-ID: <1364570381-17605-5-git-send-email-tpiepho@gmail.com> (raw)
In-Reply-To: <1364570381-17605-1-git-send-email-tpiepho@gmail.com>

Despite many warnings in the SPI documentation and code, the spi-mxs
driver sets shared chip registers in the ->setup method.  This method can
be called when transfers are in progress on other slaves controlled by the
master.  Setting registers or any other shared state will corrupt those
transfers.

So fix mxs_spi_setup() to not call mxs_spi_setup_transfer().

Now that mxs_spi_setup_transfer() won't be called with a NULL transfer,
since it's only purpose is to setup a transfer, the code can be
simplified.

mxs_spi_setup_transfer() would set the SSP SCK rate every time it was
called, which is before each transfer.  It is uncommon for the SCK rate to
change between transfers and this causes unnecessary reprogramming of the
clock registers.  Changed to only set the rate when it has changed.

This significantly speeds up short SPI messages, especially messages made
up of many transfers.  On an iMX287, using spidev with messages that
consist of 511 transfers of 4 bytes each at an SCK of 48 MHz, the
effective transfer rate more than doubles from about 290 KB/sec to 600
KB/sec.

Signed-off-by: Trent Piepho <tpiepho@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/spi/spi-mxs.c |   54 ++++++++++++++++++++++++-------------------------
 1 file changed, 26 insertions(+), 28 deletions(-)

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index fc52f78..b60baab 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -66,44 +66,47 @@
 struct mxs_spi {
 	struct mxs_ssp		ssp;
 	struct completion	c;
+	unsigned int		sck;	/* Rate requested (vs actual) */
 };
 
 static int mxs_spi_setup_transfer(struct spi_device *dev,
-				struct spi_transfer *t)
+				  const struct spi_transfer *t)
 {
 	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
 	struct mxs_ssp *ssp = &spi->ssp;
-	uint8_t bits_per_word;
-	uint32_t hz = 0;
-
-	bits_per_word = dev->bits_per_word;
-	if (t && t->bits_per_word)
-		bits_per_word = t->bits_per_word;
+	const unsigned int bits_per_word = t->bits_per_word ? : dev->bits_per_word;
+	const unsigned int hz = t->speed_hz ? min(dev->max_speed_hz, t->speed_hz) :
+					      dev->max_speed_hz;
 
 	if (bits_per_word != 8) {
-		dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n",
-					__func__, bits_per_word);
+		dev_err(&dev->dev, "Unsupported bits per word of %d\n",
+			bits_per_word);
 		return -EINVAL;
 	}
 
-	hz = dev->max_speed_hz;
-	if (t && t->speed_hz)
-		hz = min(hz, t->speed_hz);
 	if (hz == 0) {
-		dev_err(&dev->dev, "Cannot continue with zero clock\n");
+		dev_err(&dev->dev, "SPI clock rate of zero not possible\n");
 		return -EINVAL;
 	}
 
-	mxs_ssp_set_clk_rate(ssp, hz);
+	if (hz != spi->sck) {
+		mxs_ssp_set_clk_rate(ssp, hz);
+		/* Save requested value, not actual value from ssp->clk_rate.
+		 * Otherwise we would set the rate again each trasfer when
+		 * actual is not quite the same as requested.  */
+		spi->sck = hz;
+		/* Perhaps we should return an error if the actual clock is
+		 * nowhere close? */
+	}
 
 	writel(BM_SSP_CTRL0_LOCK_CS,
 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+
 	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
-		     BF_SSP_CTRL1_WORD_LENGTH
-		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
-		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
-		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
-		     ssp->base + HW_SSP_CTRL1(ssp));
+	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
+	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
+	       ssp->base + HW_SSP_CTRL1(ssp));
 
 	writel(0x0, ssp->base + HW_SSP_CMD0);
 	writel(0x0, ssp->base + HW_SSP_CMD1);
@@ -113,21 +116,16 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
 
 static int mxs_spi_setup(struct spi_device *dev)
 {
-	int err = 0;
-
 	if (!dev->bits_per_word)
 		dev->bits_per_word = 8;
 
-	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
+	if (dev->bits_per_word != 8)
 		return -EINVAL;
 
-	err = mxs_spi_setup_transfer(dev, NULL);
-	if (err) {
-		dev_err(&dev->dev,
-			"Failed to setup transfer, error = %d\n", err);
-	}
+	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
+		return -EINVAL;
 
-	return err;
+	return 0;
 }
 
 static u32 mxs_spi_cs_to_reg(unsigned cs)
-- 
1.7.10.4

  parent reply	other threads:[~2013-03-29 15:19 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-29 15:19 [PATCH 1/5] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Trent Piepho
2013-03-29 15:19 ` Trent Piepho
     [not found] ` <1364570381-17605-1-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-03-29 15:19   ` [PATCH 2/5] spi/mxs: Fix chip select control bits in DMA mode Trent Piepho
2013-03-29 15:19     ` Trent Piepho
     [not found]     ` <1364570381-17605-2-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-01 23:13       ` Marek Vasut
2013-04-01 23:13         ` Marek Vasut
     [not found]         ` <201304020113.42124.marex-ynQEQJNshbs@public.gmane.org>
2013-04-01 23:27           ` Trent Piepho
2013-04-01 23:27             ` Trent Piepho
     [not found]             ` <CA+7tXih2wAVeLpVoYkt4Tmo3h0YtLoZY3vCcv5s8sUD1u8_BVQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-01 23:30               ` Marek Vasut
2013-04-01 23:30                 ` Marek Vasut
     [not found]                 ` <201304020130.51951.marex-ynQEQJNshbs@public.gmane.org>
2013-04-01 23:40                   ` Trent Piepho
2013-04-01 23:40                     ` Trent Piepho
     [not found]                     ` <CA+7tXij_V1iAdPuPoTQ6CK6U5Y-iJprCPsTj=_LHAV1-=CL7gA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02  0:02                       ` Marek Vasut
2013-04-02  0:02                         ` Marek Vasut
     [not found]                         ` <201304020202.43501.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02  1:58                           ` Trent Piepho
2013-04-02  1:58                             ` Trent Piepho
2013-03-29 15:19   ` [PATCH 3/5] spi/mxs: Remove full duplex check, spi core already does it Trent Piepho
2013-03-29 15:19     ` Trent Piepho
2013-03-29 15:19   ` [PATCH 4/5] spi/mxs: Remove bogus setting of ssp clk rate field Trent Piepho
2013-03-29 15:19     ` Trent Piepho
     [not found]     ` <1364570381-17605-4-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-01 23:16       ` Marek Vasut
2013-04-01 23:16         ` Marek Vasut
     [not found]         ` <201304020116.04781.marex-ynQEQJNshbs@public.gmane.org>
2013-04-01 23:32           ` Trent Piepho
2013-04-01 23:32             ` Trent Piepho
     [not found]             ` <CA+7tXihhL2ETT+AgvX5KASZOOgi6bucModE88ztY9Q8U1gDbOQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-01 23:37               ` Marek Vasut
2013-04-01 23:37                 ` Marek Vasut
2013-04-02  0:07                 ` Trent Piepho
2013-04-02  0:07                   ` Trent Piepho
     [not found]                   ` <CA+7tXihfDnmkTJGzk_yvRKYwb5mJzzLJVV+XupCEGnmpQdKDLQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02  0:29                     ` Marek Vasut
2013-04-02  0:29                       ` Marek Vasut
2013-03-29 15:19   ` Trent Piepho [this message]
2013-03-29 15:19     ` [PATCH 5/5] spi/mxs: Fix multiple slave bug and don't set clock for each xfer Trent Piepho
     [not found]     ` <1364570381-17605-5-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-01 23:18       ` Marek Vasut
2013-04-01 23:18         ` Marek Vasut
2013-04-01 23:11   ` [PATCH 1/5] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Marek Vasut
2013-04-01 23:11     ` Marek Vasut
     [not found]     ` <201304020111.13969.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02  1:24       ` Trent Piepho
2013-04-02  1:24         ` Trent Piepho
     [not found]         ` <CA+7tXigx=qcDDJZGAx7JEX+Y-CDG-B0xyYgs6fHbUZofH7gnKw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02  4:22           ` Marek Vasut
2013-04-02  4:22             ` Marek Vasut
     [not found]             ` <201304020622.52429.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02  7:11               ` Trent Piepho
2013-04-02  7:11                 ` Trent Piepho
     [not found]                 ` <CA+7tXigvg+5k0Baa12CVwP5Ar7HUsJ8ihB19xrav4CNA6ZMFiA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02 10:32                   ` Marek Vasut
2013-04-02 10:32                     ` Marek Vasut
     [not found]                     ` <201304021232.12736.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02 12:40                       ` Trent Piepho
2013-04-02 12:40                         ` Trent Piepho
     [not found]                         ` <CA+7tXii8xhZQeKU2dTN26LxySNXhJT9NgRXcJ21cOX64qYj1NA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02 23:39                           ` Marek Vasut
2013-04-02 23:39                             ` Marek Vasut

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