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From: Rahul Sharma <rahul.sharma@samsung.com>
To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: mturquette@linaro.org, kgene.kim@samsung.com,
	inki.dae@samsung.com, s.nawrocki@samsung.com,
	thomas.abraham@linaro.org, tomasz.figa@gmail.com,
	joshi@samsung.com, r.sh.open@gmail.com,
	Rahul Sharma <rahul.sharma@samsung.com>
Subject: [PATCH v4 3/5] clk/exynos5420: fix the order of parents of hdmi mux
Date: Thu, 29 Aug 2013 11:07:07 +0530	[thread overview]
Message-ID: <1377754629-31465-4-git-send-email-rahul.sharma@samsung.com> (raw)
In-Reply-To: <1377754629-31465-1-git-send-email-rahul.sharma@samsung.com>

Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 4e0c13e..522c033 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -286,7 +286,7 @@ PNAME(audio2_p)	= { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
 		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 PNAME(spdif_p)	= { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
 		  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)	= { "sclk_hdmiphy", "dout_hdmi_pixel" };
+PNAME(hdmi_p)	= { "dout_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(maudio0_p)	= { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
 			  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 
-- 
1.7.10.4

WARNING: multiple messages have this Message-ID (diff)
From: rahul.sharma@samsung.com (Rahul Sharma)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 3/5] clk/exynos5420: fix the order of parents of hdmi mux
Date: Thu, 29 Aug 2013 11:07:07 +0530	[thread overview]
Message-ID: <1377754629-31465-4-git-send-email-rahul.sharma@samsung.com> (raw)
In-Reply-To: <1377754629-31465-1-git-send-email-rahul.sharma@samsung.com>

Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 4e0c13e..522c033 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -286,7 +286,7 @@ PNAME(audio2_p)	= { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
 		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 PNAME(spdif_p)	= { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
 		  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)	= { "sclk_hdmiphy", "dout_hdmi_pixel" };
+PNAME(hdmi_p)	= { "dout_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(maudio0_p)	= { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
 			  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 
-- 
1.7.10.4

  parent reply	other threads:[~2013-08-29  5:15 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-29  5:37 [PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem Rahul Sharma
2013-08-29  5:37 ` Rahul Sharma
2013-08-29  5:37 ` [PATCH v4 1/5] clk/exynos5420: add sclk_hdmiphy to the list of special clocks Rahul Sharma
2013-08-29  5:37   ` Rahul Sharma
2013-08-29  5:37 ` [PATCH v4 2/5] clk/exynos5420: add gate clock for mixer sysmmu Rahul Sharma
2013-08-29  5:37   ` Rahul Sharma
2013-08-29  5:37 ` Rahul Sharma [this message]
2013-08-29  5:37   ` [PATCH v4 3/5] clk/exynos5420: fix the order of parents of hdmi mux Rahul Sharma
2013-08-29  5:37 ` [PATCH v4 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver Rahul Sharma
2013-08-29  5:37   ` Rahul Sharma
2013-08-29  5:37 ` [PATCH v4 5/5] clk/exynos5420: assign dout_pixel id to pixel clock divider Rahul Sharma
2013-08-29  5:37   ` Rahul Sharma
2013-08-29 12:30 ` [PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem Tomasz Figa
2013-08-29 12:30   ` Tomasz Figa
2013-08-29 13:36   ` Rahul Sharma
2013-08-29 13:36     ` Rahul Sharma
2013-08-30  1:04     ` Mike Turquette
2013-08-30  1:04       ` Mike Turquette

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