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From: Alexander Graf <agraf@suse.de>
To: "\"" <kvm-ppc@vger.kernel.org>, " <kvm-ppc@vger.kernel.org>"@suse.de
Cc: "kvm@vger.kernel.org mailing list" <kvm@vger.kernel.org>
Subject: [PATCH 4/4] KVM: PPC: Book3S: PR: Enable interrupts earlier
Date: Fri, 29 Nov 2013 03:55:01 +0100	[thread overview]
Message-ID: <1385693701-27632-5-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1385693701-27632-1-git-send-email-agraf@suse.de>

Now that the svcpu sync is interrupt aware we can enable interrupts
earlier in the exit code path again, moving 32bit and 64bit closer
together.

While at it, document the fact that we're always executing the exit
path with interrupts enabled so that the next person doesn't trap
over this.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/kvm/book3s_interrupts.S | 6 +-----
 arch/powerpc/kvm/book3s_rmhandlers.S | 6 +-----
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S
index 2f7d571..a8cc2b2 100644
--- a/arch/powerpc/kvm/book3s_interrupts.S
+++ b/arch/powerpc/kvm/book3s_interrupts.S
@@ -129,6 +129,7 @@ kvm_start_lightweight:
 	 * R12      = exit handler id
 	 * R13      = PACA
 	 * SVCPU.*  = guest *
+	 * MSR.EE   = 1
 	 *
 	 */
 
@@ -149,11 +150,6 @@ kvm_start_lightweight:
 	nop
 
 #ifdef CONFIG_PPC_BOOK3S_64
-	/* Re-enable interrupts */
-	ld	r3, HSTATE_HOST_MSR(r13)
-	ori	r3, r3, MSR_EE
-	MTMSR_EERI(r3)
-
 	/*
 	 * Reload kernel SPRG3 value.
 	 * No need to save guest value as usermode can't modify SPRG3.
diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S
index a38c4c9..c3c5231 100644
--- a/arch/powerpc/kvm/book3s_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_rmhandlers.S
@@ -153,15 +153,11 @@ _GLOBAL(kvmppc_entry_trampoline)
 
 	li	r6, MSR_IR | MSR_DR
 	andc	r6, r5, r6	/* Clear DR and IR in MSR value */
-#ifdef CONFIG_PPC_BOOK3S_32
 	/*
 	 * Set EE in HOST_MSR so that it's enabled when we get into our
-	 * C exit handler function.  On 64-bit we delay enabling
-	 * interrupts until we have finished transferring stuff
-	 * to or from the PACA.
+	 * C exit handler function.
 	 */
 	ori	r5, r5, MSR_EE
-#endif
 	mtsrr0	r7
 	mtsrr1	r6
 	RFI
-- 
1.8.1.4

WARNING: multiple messages have this Message-ID (diff)
From: Alexander Graf <agraf@suse.de>
To: "\"" <kvm-ppc@vger.kernel.org>, " <kvm-ppc@vger.kernel.org>"@suse.de
Cc: "kvm@vger.kernel.org mailing list" <kvm@vger.kernel.org>
Subject: [PATCH 4/4] KVM: PPC: Book3S: PR: Enable interrupts earlier
Date: Fri, 29 Nov 2013 02:55:01 +0000	[thread overview]
Message-ID: <1385693701-27632-5-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1385693701-27632-1-git-send-email-agraf@suse.de>

Now that the svcpu sync is interrupt aware we can enable interrupts
earlier in the exit code path again, moving 32bit and 64bit closer
together.

While at it, document the fact that we're always executing the exit
path with interrupts enabled so that the next person doesn't trap
over this.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/kvm/book3s_interrupts.S | 6 +-----
 arch/powerpc/kvm/book3s_rmhandlers.S | 6 +-----
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S
index 2f7d571..a8cc2b2 100644
--- a/arch/powerpc/kvm/book3s_interrupts.S
+++ b/arch/powerpc/kvm/book3s_interrupts.S
@@ -129,6 +129,7 @@ kvm_start_lightweight:
 	 * R12      = exit handler id
 	 * R13      = PACA
 	 * SVCPU.*  = guest *
+	 * MSR.EE   = 1
 	 *
 	 */
 
@@ -149,11 +150,6 @@ kvm_start_lightweight:
 	nop
 
 #ifdef CONFIG_PPC_BOOK3S_64
-	/* Re-enable interrupts */
-	ld	r3, HSTATE_HOST_MSR(r13)
-	ori	r3, r3, MSR_EE
-	MTMSR_EERI(r3)
-
 	/*
 	 * Reload kernel SPRG3 value.
 	 * No need to save guest value as usermode can't modify SPRG3.
diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S
index a38c4c9..c3c5231 100644
--- a/arch/powerpc/kvm/book3s_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_rmhandlers.S
@@ -153,15 +153,11 @@ _GLOBAL(kvmppc_entry_trampoline)
 
 	li	r6, MSR_IR | MSR_DR
 	andc	r6, r5, r6	/* Clear DR and IR in MSR value */
-#ifdef CONFIG_PPC_BOOK3S_32
 	/*
 	 * Set EE in HOST_MSR so that it's enabled when we get into our
-	 * C exit handler function.  On 64-bit we delay enabling
-	 * interrupts until we have finished transferring stuff
-	 * to or from the PACA.
+	 * C exit handler function.
 	 */
 	ori	r5, r5, MSR_EE
-#endif
 	mtsrr0	r7
 	mtsrr1	r6
 	RFI
-- 
1.8.1.4


  parent reply	other threads:[~2013-11-29  2:55 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-29  2:54 [PATCH 0/4] KVM: PPC: Book3S: PR: Fix with CONFIG_PREEMPT=y Alexander Graf
2013-11-29  2:54 ` Alexander Graf
2013-11-29  2:54 ` [PATCH 1/4] KVM: PPC: Book3S: PR: Don't clobber our exit handler id Alexander Graf
2013-11-29  2:54   ` Alexander Graf
2013-11-30  7:20   ` Paul Mackerras
2013-11-30  7:20     ` Paul Mackerras
2013-11-30 12:38     ` Alexander Graf
2013-11-30 12:38       ` Alexander Graf
2013-11-29  2:54 ` [PATCH 2/4] KVM: PPC: Book3S: PR: Export kvmppc_copy_to|from_svcpu Alexander Graf
2013-11-29  2:54   ` Alexander Graf
2013-11-29  2:55 ` [PATCH 3/4] KVM: PPC: Book3S: PR: Make svcpu -> vcpu store preempt savvy Alexander Graf
2013-11-29  2:55   ` Alexander Graf
2013-11-29  2:55 ` Alexander Graf [this message]
2013-11-29  2:55   ` [PATCH 4/4] KVM: PPC: Book3S: PR: Enable interrupts earlier Alexander Graf

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