From: Marek Vasut <marex@denx.de> To: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Marek Vasut <marex@denx.de>, Bjorn Helgaas <bhelgaas@google.com>, Frank Li <lznuaa@gmail.com>, Harro Haan <hrhaan@gmail.com>, Jingoo Han <jg1.han@samsung.com>, Mohit KUMAR <Mohit.KUMAR@st.com>, Pratyush Anand <pratyush.anand@st.com>, Richard Zhu <r65037@freescale.com>, Sascha Hauer <s.hauer@pengutronix.de>, Sean Cross <xobs@kosagi.com>, Shawn Guo <shawn.guo@linaro.org>, Siva Reddy Kallam <siva.kallam@samsung.com>, Srikanth T Shivanand <ts.srikanth@samsung.com>, Tim Harvey <tharvey@gateworks.com>, Troy Kisky <troy.kisky@boundarydevices.com>, Yinghai Lu <yinghai@kernel.org> Subject: [PATCH 2/7] PCI: imx6: Fix waiting for link up Date: Wed, 11 Dec 2013 11:30:13 +0100 [thread overview] Message-ID: <1386757818-5154-2-git-send-email-marex@denx.de> (raw) In-Reply-To: <1386757818-5154-1-git-send-email-marex@denx.de> While waiting for the PHY to report the PCIe link is up, we might hit a situation where the link training is still in progress, while the PHY already reports the link is up. Add additional check for this condition. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Frank Li <lznuaa@gmail.com> Cc: Harro Haan <hrhaan@gmail.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Richard Zhu <r65037@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Siva Reddy Kallam <siva.kallam@samsung.com> Cc: Srikanth T Shivanand <ts.srikanth@samsung.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Yinghai Lu <yinghai@kernel.org> --- drivers/pci/host/pci-imx6.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 52027ad..4d5be4e 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -48,6 +48,8 @@ struct imx6_pcie { #define PL_OFFSET 0x700 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -338,10 +340,17 @@ static int imx6_pcie_link_up(struct pcie_port *pp) { u32 rc, ltssm, rx_valid, temp; - /* link is debug bit 36, debug register 1 starts at bit 32 */ - rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); - if (rc) - return -EAGAIN; + /* + * Test if the PHY reports that the link is up and also that + * the link training finished. It might happen that the PHY + * reports the link is already up, but the link training bit + * is still set, so make sure to check the training is done + * as well here. + */ + rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) + return 1; /* * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. -- 1.8.4.3
WARNING: multiple messages have this Message-ID (diff)
From: marex@denx.de (Marek Vasut) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/7] PCI: imx6: Fix waiting for link up Date: Wed, 11 Dec 2013 11:30:13 +0100 [thread overview] Message-ID: <1386757818-5154-2-git-send-email-marex@denx.de> (raw) In-Reply-To: <1386757818-5154-1-git-send-email-marex@denx.de> While waiting for the PHY to report the PCIe link is up, we might hit a situation where the link training is still in progress, while the PHY already reports the link is up. Add additional check for this condition. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Frank Li <lznuaa@gmail.com> Cc: Harro Haan <hrhaan@gmail.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Richard Zhu <r65037@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Siva Reddy Kallam <siva.kallam@samsung.com> Cc: Srikanth T Shivanand <ts.srikanth@samsung.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Yinghai Lu <yinghai@kernel.org> --- drivers/pci/host/pci-imx6.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 52027ad..4d5be4e 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -48,6 +48,8 @@ struct imx6_pcie { #define PL_OFFSET 0x700 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -338,10 +340,17 @@ static int imx6_pcie_link_up(struct pcie_port *pp) { u32 rc, ltssm, rx_valid, temp; - /* link is debug bit 36, debug register 1 starts@bit 32 */ - rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); - if (rc) - return -EAGAIN; + /* + * Test if the PHY reports that the link is up and also that + * the link training finished. It might happen that the PHY + * reports the link is already up, but the link training bit + * is still set, so make sure to check the training is done + * as well here. + */ + rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) + return 1; /* * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. -- 1.8.4.3
next prev parent reply other threads:[~2013-12-11 10:30 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-12-11 10:30 [PATCH 1/7] PCI: imx6: Make reset-gpio optional Marek Vasut 2013-12-11 10:30 ` Marek Vasut 2013-12-11 10:30 ` Marek Vasut [this message] 2013-12-11 10:30 ` [PATCH 2/7] PCI: imx6: Fix waiting for link up Marek Vasut 2013-12-11 10:30 ` [PATCH V2 3/7] PCI: imx6: Split away the PHY reset Marek Vasut 2013-12-11 10:30 ` Marek Vasut 2013-12-19 1:11 ` Jingoo Han 2013-12-19 1:11 ` Jingoo Han 2013-12-11 10:30 ` [PATCH 4/7] PCI: imx6: Split away the link up wait loop Marek Vasut 2013-12-11 10:30 ` Marek Vasut 2013-12-11 10:30 ` [PATCH V2 5/7] PCI: imx6: Fix link start operation Marek Vasut 2013-12-11 10:30 ` Marek Vasut 2013-12-11 10:30 ` [PATCH 6/7] PCI: imx6: Fix bugs in PCIe startup code Marek Vasut 2013-12-11 10:30 ` Marek Vasut 2013-12-11 10:30 ` [PATCH 7/7] ARM: dts: imx6q-sabrelite: Enable PCI express Marek Vasut 2013-12-11 10:30 ` Marek Vasut 2013-12-13 7:01 ` Shawn Guo 2013-12-13 7:01 ` Shawn Guo 2013-12-12 2:46 ` [PATCH 1/7] PCI: imx6: Make reset-gpio optional Jingoo Han 2013-12-12 2:46 ` Jingoo Han 2013-12-12 5:10 ` Tim Harvey 2013-12-12 5:10 ` Tim Harvey 2013-12-12 10:22 ` Marek Vasut 2013-12-12 10:22 ` Marek Vasut 2013-12-12 18:16 ` Tim Harvey 2013-12-12 18:16 ` Tim Harvey 2013-12-12 18:25 ` Marek Vasut 2013-12-12 18:25 ` Marek Vasut 2013-12-12 21:07 ` Bjorn Helgaas 2013-12-12 21:07 ` Bjorn Helgaas 2013-12-12 21:20 ` Bjorn Helgaas 2013-12-12 21:20 ` Bjorn Helgaas 2013-12-12 21:38 ` Marek Vasut 2013-12-12 21:38 ` Marek Vasut 2013-12-12 22:12 ` Harro Haan 2013-12-12 22:12 ` Harro Haan 2013-12-12 21:49 [PATCH V2 " Marek Vasut 2013-12-12 21:49 ` [PATCH 2/7] PCI: imx6: Fix waiting for link up Marek Vasut 2013-12-12 21:49 ` Marek Vasut
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