From: Abhilash Kesavan <a.kesavan@samsung.com>
To: dianders@chromium.org, olof@lixom.net, kgene.kim@samsung.com,
jonghwa3.lee@samsung.com, yadi.brar@samsung.com,
mturquette@linaro.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org,
devicetree-discuss@lists.ozlabs.org
Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Subject: [PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks
Date: Wed, 11 Dec 2013 17:27:06 +0530 [thread overview]
Message-ID: <1386763029-8516-3-git-send-email-a.kesavan@samsung.com> (raw)
In-Reply-To: <1386763029-8516-1-git-send-email-a.kesavan@samsung.com>
For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
to be low initially for normal mode on Exynos5250.
Also fix the corresponding AFTR and LPA configurations.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-exynos/pmu.c | 66 ++++++++++++++++++++++++++++++++------------
1 file changed, 48 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d6885..5f4d26b 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
- { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
- { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ PMU_TABLE_END,},
};
@@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ISP_ARM_OPTION,
};
+void __iomem *exynos5_list_disable_pmu_reg[] = {
+ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,
+};
+
static void exynos5_init_pmu(void)
{
unsigned int i;
@@ -391,6 +412,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
static int __init exynos_pmu_init(void)
{
unsigned int value;
+ unsigned int i;
exynos_pmu_config = exynos4210_pmu_config;
@@ -413,6 +435,14 @@ static int __init exynos_pmu_init(void)
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+ /*
+ * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers for
+ * local power blocks to Low initially as per the "System-Level
+ * Power-Down Configuration Registers" table.
+ */
+ for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++)
+ __raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);
+
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
} else {
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: a.kesavan@samsung.com (Abhilash Kesavan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks
Date: Wed, 11 Dec 2013 17:27:06 +0530 [thread overview]
Message-ID: <1386763029-8516-3-git-send-email-a.kesavan@samsung.com> (raw)
In-Reply-To: <1386763029-8516-1-git-send-email-a.kesavan@samsung.com>
For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
to be low initially for normal mode on Exynos5250.
Also fix the corresponding AFTR and LPA configurations.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-exynos/pmu.c | 66 ++++++++++++++++++++++++++++++++------------
1 file changed, 48 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d6885..5f4d26b 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
- { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
- { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
- { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+ { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ PMU_TABLE_END,},
};
@@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ISP_ARM_OPTION,
};
+void __iomem *exynos5_list_disable_pmu_reg[] = {
+ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,
+ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,
+};
+
static void exynos5_init_pmu(void)
{
unsigned int i;
@@ -391,6 +412,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
static int __init exynos_pmu_init(void)
{
unsigned int value;
+ unsigned int i;
exynos_pmu_config = exynos4210_pmu_config;
@@ -413,6 +435,14 @@ static int __init exynos_pmu_init(void)
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+ /*
+ * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers for
+ * local power blocks to Low initially as per the "System-Level
+ * Power-Down Configuration Registers" table.
+ */
+ for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++)
+ __raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);
+
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
} else {
--
1.7.9.5
next prev parent reply other threads:[~2013-12-11 11:56 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-11 11:57 [PATCH 0/5] Power Related Fixes for Exynos5250 Abhilash Kesavan
2013-12-11 11:57 ` Abhilash Kesavan
2013-12-11 11:57 ` [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock Abhilash Kesavan
2013-12-11 11:57 ` Abhilash Kesavan
2013-12-11 23:55 ` Doug Anderson
2013-12-11 23:55 ` Doug Anderson
2013-12-12 0:13 ` Tomasz Figa
2013-12-12 0:13 ` Tomasz Figa
2013-12-12 0:30 ` Doug Anderson
2013-12-12 0:30 ` Doug Anderson
2013-12-12 4:36 ` Abhilash Kesavan
2013-12-12 4:36 ` Abhilash Kesavan
2013-12-12 9:53 ` Tomasz Figa
2013-12-12 9:53 ` Tomasz Figa
2013-12-30 17:49 ` Tomasz Figa
2013-12-30 17:49 ` Tomasz Figa
2013-12-11 11:57 ` Abhilash Kesavan [this message]
2013-12-11 11:57 ` [PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks Abhilash Kesavan
2013-12-11 12:29 ` Tomasz Figa
2013-12-11 12:29 ` Tomasz Figa
2013-12-12 2:43 ` Abhilash Kesavan
2013-12-12 2:43 ` Abhilash Kesavan
2013-12-11 11:57 ` [PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back Abhilash Kesavan
2013-12-11 11:57 ` Abhilash Kesavan
2013-12-11 12:24 ` Tomasz Figa
2013-12-11 12:24 ` Tomasz Figa
2013-12-12 2:47 ` Abhilash Kesavan
2013-12-12 2:47 ` Abhilash Kesavan
2013-12-11 11:57 ` [PATCH 4/5] ARM: EXYNOS5250: Implement pm_power_off Abhilash Kesavan
2013-12-11 11:57 ` Abhilash Kesavan
2013-12-11 11:57 ` [PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686 Abhilash Kesavan
2013-12-11 11:57 ` Abhilash Kesavan
2013-12-11 23:57 ` Doug Anderson
2013-12-11 23:57 ` Doug Anderson
2013-12-12 2:50 ` Abhilash Kesavan
2013-12-12 2:50 ` Abhilash Kesavan
2013-12-11 12:41 ` [PATCH 0/5] Power Related Fixes for Exynos5250 Tomasz Figa
2013-12-11 12:41 ` Tomasz Figa
2013-12-12 2:42 ` Abhilash Kesavan
2013-12-12 2:42 ` Abhilash Kesavan
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