All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
To: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Sean Cross <xobs-nXMMniAx+RbQT0dZR+AlfA@public.gmane.org>,
	Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>,
	Richard Zhu <r65037-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
	Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
	Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Ian Campbell
	<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>,
	kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org
Subject: [PATCH 7/8] PCI: designware: make MSI isr shared irq aware
Date: Fri, 28 Mar 2014 17:52:58 +0100	[thread overview]
Message-ID: <1396025579-14344-8-git-send-email-l.stach@pengutronix.de> (raw)
In-Reply-To: <1396025579-14344-1-git-send-email-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>

On i.MX6 the host controller MSI irq is shared
with PCI legacy INTD. Make sure we don't bail too
early from the irq handler.

The issue is fairly theoretical as it would require
a system setup with a PCIe switch where one connected
device is using legacy INTD and another one using
MSI, but better fix it now.

Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 drivers/pci/host/pci-exynos.c      | 4 +---
 drivers/pci/host/pcie-designware.c | 6 +++++-
 drivers/pci/host/pcie-designware.h | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 3de6bfbbe8e9..b616d34922d8 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -415,9 +415,7 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
 {
 	struct pcie_port *pp = arg;
 
-	dw_handle_msi_irq(pp);
-
-	return IRQ_HANDLED;
+	return dw_handle_msi_irq(pp);
 }
 
 static void exynos_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 98c118e04dba..cbce9b04b13d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -156,15 +156,17 @@ static struct irq_chip dw_msi_irq_chip = {
 };
 
 /* MSI int handler */
-void dw_handle_msi_irq(struct pcie_port *pp)
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
 	unsigned long val;
 	int i, pos, irq;
+	irqreturn_t ret = IRQ_NONE;
 
 	for (i = 0; i < MAX_MSI_CTRLS; i++) {
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
 				(u32 *)&val);
 		if (val) {
+			ret = IRQ_HANDLED;
 			pos = 0;
 			while ((pos = find_next_bit(&val, 32, pos)) != 32) {
 				irq = irq_find_mapping(pp->irq_domain,
@@ -177,6 +179,8 @@ void dw_handle_msi_irq(struct pcie_port *pp)
 			}
 		}
 	}
+
+	return ret;
 }
 
 void dw_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 3063b3594d88..a169d22d517e 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -68,7 +68,7 @@ struct pcie_host_ops {
 
 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
-void dw_handle_msi_irq(struct pcie_port *pp);
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
-- 
1.9.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

WARNING: multiple messages have this Message-ID (diff)
From: Lucas Stach <l.stach@pengutronix.de>
To: linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	Sean Cross <xobs@kosagi.com>, Marek Vasut <marex@denx.de>,
	Richard Zhu <r65037@freescale.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jingoo Han <jg1.han@samsung.com>,
	Shawn Guo <shawn.guo@linaro.org>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Mark Rutland <mark.rutland@arm.com>,
	Pawel Moll <pawel.moll@arm.com>, Rob Herring <robh+dt@kernel.org>,
	Arnd Bergmann <arnd@arndb.de>, Tim Harvey <tharvey@gateworks.com>,
	kernel@pengutronix.de
Subject: [PATCH 7/8] PCI: designware: make MSI isr shared irq aware
Date: Fri, 28 Mar 2014 17:52:58 +0100	[thread overview]
Message-ID: <1396025579-14344-8-git-send-email-l.stach@pengutronix.de> (raw)
In-Reply-To: <1396025579-14344-1-git-send-email-l.stach@pengutronix.de>

On i.MX6 the host controller MSI irq is shared
with PCI legacy INTD. Make sure we don't bail too
early from the irq handler.

The issue is fairly theoretical as it would require
a system setup with a PCIe switch where one connected
device is using legacy INTD and another one using
MSI, but better fix it now.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/host/pci-exynos.c      | 4 +---
 drivers/pci/host/pcie-designware.c | 6 +++++-
 drivers/pci/host/pcie-designware.h | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 3de6bfbbe8e9..b616d34922d8 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -415,9 +415,7 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
 {
 	struct pcie_port *pp = arg;
 
-	dw_handle_msi_irq(pp);
-
-	return IRQ_HANDLED;
+	return dw_handle_msi_irq(pp);
 }
 
 static void exynos_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 98c118e04dba..cbce9b04b13d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -156,15 +156,17 @@ static struct irq_chip dw_msi_irq_chip = {
 };
 
 /* MSI int handler */
-void dw_handle_msi_irq(struct pcie_port *pp)
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
 	unsigned long val;
 	int i, pos, irq;
+	irqreturn_t ret = IRQ_NONE;
 
 	for (i = 0; i < MAX_MSI_CTRLS; i++) {
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
 				(u32 *)&val);
 		if (val) {
+			ret = IRQ_HANDLED;
 			pos = 0;
 			while ((pos = find_next_bit(&val, 32, pos)) != 32) {
 				irq = irq_find_mapping(pp->irq_domain,
@@ -177,6 +179,8 @@ void dw_handle_msi_irq(struct pcie_port *pp)
 			}
 		}
 	}
+
+	return ret;
 }
 
 void dw_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 3063b3594d88..a169d22d517e 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -68,7 +68,7 @@ struct pcie_host_ops {
 
 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
-void dw_handle_msi_irq(struct pcie_port *pp);
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
-- 
1.9.0


WARNING: multiple messages have this Message-ID (diff)
From: l.stach@pengutronix.de (Lucas Stach)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 7/8] PCI: designware: make MSI isr shared irq aware
Date: Fri, 28 Mar 2014 17:52:58 +0100	[thread overview]
Message-ID: <1396025579-14344-8-git-send-email-l.stach@pengutronix.de> (raw)
In-Reply-To: <1396025579-14344-1-git-send-email-l.stach@pengutronix.de>

On i.MX6 the host controller MSI irq is shared
with PCI legacy INTD. Make sure we don't bail too
early from the irq handler.

The issue is fairly theoretical as it would require
a system setup with a PCIe switch where one connected
device is using legacy INTD and another one using
MSI, but better fix it now.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/host/pci-exynos.c      | 4 +---
 drivers/pci/host/pcie-designware.c | 6 +++++-
 drivers/pci/host/pcie-designware.h | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 3de6bfbbe8e9..b616d34922d8 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -415,9 +415,7 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
 {
 	struct pcie_port *pp = arg;
 
-	dw_handle_msi_irq(pp);
-
-	return IRQ_HANDLED;
+	return dw_handle_msi_irq(pp);
 }
 
 static void exynos_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 98c118e04dba..cbce9b04b13d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -156,15 +156,17 @@ static struct irq_chip dw_msi_irq_chip = {
 };
 
 /* MSI int handler */
-void dw_handle_msi_irq(struct pcie_port *pp)
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
 	unsigned long val;
 	int i, pos, irq;
+	irqreturn_t ret = IRQ_NONE;
 
 	for (i = 0; i < MAX_MSI_CTRLS; i++) {
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
 				(u32 *)&val);
 		if (val) {
+			ret = IRQ_HANDLED;
 			pos = 0;
 			while ((pos = find_next_bit(&val, 32, pos)) != 32) {
 				irq = irq_find_mapping(pp->irq_domain,
@@ -177,6 +179,8 @@ void dw_handle_msi_irq(struct pcie_port *pp)
 			}
 		}
 	}
+
+	return ret;
 }
 
 void dw_pcie_msi_init(struct pcie_port *pp)
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 3063b3594d88..a169d22d517e 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -68,7 +68,7 @@ struct pcie_host_ops {
 
 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
-void dw_handle_msi_irq(struct pcie_port *pp);
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
-- 
1.9.0

  parent reply	other threads:[~2014-03-28 16:52 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-28 16:52 [PATCH 0/8] i.MX6 PCIe binding change and MSI support Lucas Stach
2014-03-28 16:52 ` Lucas Stach
2014-03-28 16:52 ` [PATCH 1/8] ARM: imx6q-clk: parent lvds_gate from lvds_sel Lucas Stach
2014-03-28 16:52   ` Lucas Stach
2014-03-30 17:29   ` Marek Vasut
2014-03-30 17:29     ` Marek Vasut
     [not found]   ` <1396025579-14344-2-git-send-email-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-04-02 12:57     ` Hong-Xing.Zhu-KZfg59tc24xl57MIdRCFDg
2014-04-02 12:57       ` Hong-Xing.Zhu at freescale.com
2014-04-02 12:57       ` Hong-Xing.Zhu
2014-04-03  6:49   ` Shawn Guo
2014-04-03  6:49     ` Shawn Guo
2014-04-03  6:49     ` Shawn Guo
2014-03-28 16:52 ` [PATCH 2/8] PCI: designware: split Exynos and i.MX bindings Lucas Stach
2014-03-28 16:52   ` Lucas Stach
2014-03-30 17:36   ` Marek Vasut
2014-03-30 17:36     ` Marek Vasut
2014-03-31  9:28     ` Lucas Stach
2014-03-31  9:28       ` Lucas Stach
2014-03-31  9:36       ` Marek Vasut
2014-03-31  9:36         ` Marek Vasut
2014-03-31 10:38         ` Lucas Stach
2014-03-31 10:38           ` Lucas Stach
2014-03-31 10:52           ` Marek Vasut
2014-03-31 10:52             ` Marek Vasut
2014-03-28 16:52 ` [PATCH 3/8] ARM: dts: imx6: update pcie to bring in line with new binding Lucas Stach
2014-03-28 16:52   ` Lucas Stach
2014-04-30  6:02   ` Shawn Guo
2014-04-30  6:02     ` Shawn Guo
2014-04-30  6:02     ` Shawn Guo
2014-04-30 10:17     ` Lucas Stach
2014-04-30 10:17       ` Lucas Stach
2014-03-28 16:52 ` [PATCH 5/8] PCI: imx6: drop old irq mapping Lucas Stach
2014-03-28 16:52   ` Lucas Stach
2014-03-28 16:52 ` [PATCH 6/8] PCI: imx6: rip out optional (and unused) irqs Lucas Stach
2014-03-28 16:52   ` Lucas Stach
     [not found] ` <1396025579-14344-1-git-send-email-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-03-28 16:52   ` [PATCH 4/8] PCI: imx6: use new clock names Lucas Stach
2014-03-28 16:52     ` Lucas Stach
2014-03-28 16:52     ` Lucas Stach
2014-04-03  6:50     ` Shawn Guo
2014-04-03  6:50       ` Shawn Guo
2014-04-03  6:50       ` Shawn Guo
2014-04-03  8:21       ` Lucas Stach
2014-04-03  8:21         ` Lucas Stach
2014-04-03  8:21         ` Lucas Stach
     [not found]         ` <1396513265.5057.7.camel-WzVe3FnzCwFR6QfukMTsflXZhhPuCNm+@public.gmane.org>
2014-04-03  8:51           ` Lucas Stach
2014-04-03  8:51             ` Lucas Stach
2014-04-03  8:51             ` Lucas Stach
2014-03-28 16:52   ` Lucas Stach [this message]
2014-03-28 16:52     ` [PATCH 7/8] PCI: designware: make MSI isr shared irq aware Lucas Stach
2014-03-28 16:52     ` Lucas Stach
2014-04-28  2:14     ` Jingoo Han
2014-04-28  2:14       ` Jingoo Han
2014-03-28 16:52 ` [PATCH 8/8] PCI: imx6: add support for MSI Lucas Stach
2014-03-28 16:52   ` Lucas Stach
2014-03-30 17:41 ` [PATCH 0/8] i.MX6 PCIe binding change and MSI support Marek Vasut
2014-03-30 17:41   ` Marek Vasut
2014-04-24 17:58 ` Bjorn Helgaas
2014-04-24 17:58   ` Bjorn Helgaas
2014-04-25 10:21   ` Lucas Stach
2014-04-25 10:21     ` Lucas Stach
2014-04-25 14:39     ` Bjorn Helgaas
2014-04-25 14:39       ` Bjorn Helgaas
2014-04-25 15:04       ` Hong-Xing.Zhu
2014-04-25 15:04         ` Hong-Xing.Zhu at freescale.com
2014-04-25 15:04         ` Hong-Xing.Zhu
2014-04-29 12:31       ` Lucas Stach
2014-04-29 12:31         ` Lucas Stach
2014-05-12  8:59         ` Lucas Stach
2014-05-12  8:59           ` Lucas Stach
2014-05-27 14:02           ` Fabio Estevam
2014-05-27 14:02             ` Fabio Estevam
2014-05-30 17:30           ` Bjorn Helgaas
2014-05-30 17:30             ` Bjorn Helgaas
     [not found]             ` <20140530173053.GF4607-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2014-06-03 13:22               ` Lucas Stach
2014-06-03 13:22                 ` Lucas Stach
2014-06-03 13:22                 ` Lucas Stach
2014-06-03 14:50                 ` Bjorn Helgaas
2014-06-03 14:50                   ` Bjorn Helgaas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1396025579-14344-8-git-send-email-l.stach@pengutronix.de \
    --to=l.stach-bicnvbalz9megne8c9+irq@public.gmane.org \
    --cc=arnd-r2nGTMty4D4@public.gmane.org \
    --cc=bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org \
    --cc=devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
    --cc=ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org \
    --cc=jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org \
    --cc=kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org \
    --cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
    --cc=linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
    --cc=linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
    --cc=marex-ynQEQJNshbs@public.gmane.org \
    --cc=mark.rutland-5wv7dgnIgG8@public.gmane.org \
    --cc=pawel.moll-5wv7dgnIgG8@public.gmane.org \
    --cc=r65037-KZfg59tc24xl57MIdRCFDg@public.gmane.org \
    --cc=robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \
    --cc=shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org \
    --cc=tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org \
    --cc=xobs-nXMMniAx+RbQT0dZR+AlfA@public.gmane.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.