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From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2] drm/i915/chv: Freq(opcode) request for CHV.
Date: Mon, 12 May 2014 19:23:03 +0530	[thread overview]
Message-ID: <1399902783-5947-1-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1399294059-20748-11-git-send-email-deepak.s@linux.intel.com>

From: Deepak S <deepak.s@linux.intel.com>

On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.

v2: Avoid vairable for freq request (ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6af51ad..56e93e8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1161,8 +1161,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 		if (adj > 0)
 			adj *= 2;
-		else
-			adj = 1;
+		else {
+			/* CHV needs even encode values */
+			adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
+		}
 		new_delay = dev_priv->rps.cur_freq + adj;
 
 		/*
@@ -1180,8 +1182,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
 		if (adj < 0)
 			adj *= 2;
-		else
-			adj = -1;
+		else {
+			/* CHV needs even encode values */
+			adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
+		}
 		new_delay = dev_priv->rps.cur_freq + adj;
 	} else { /* unknown event */
 		new_delay = dev_priv->rps.cur_freq;
-- 
1.9.1

  parent reply	other threads:[~2014-05-12 13:53 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-05 12:47 [PATCH 00/10] Enable RC6/Turbo on CHV deepak.s
2014-05-05 12:47 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-05-07 13:58   ` Ville Syrjälä
2014-05-05 12:47 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-05-07 14:08   ` Ville Syrjälä
2014-05-14 15:37   ` [PATCH v3] " deepak.s
2014-05-14 15:47     ` Ville Syrjälä
2014-05-05 12:47 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-09 13:19   ` Mika Kuoppala
2014-05-14 15:47     ` Deepak S
2014-05-15  9:57   ` [PATCH v5] " deepak.s
2014-05-15 10:00     ` Deepak S
2014-05-15 10:16     ` Mika Kuoppala
2014-05-15 10:22       ` Mika Kuoppala
2014-05-15 12:38       ` [PATCH v5 1/8] " deepak.s
2014-05-05 12:47 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-05-16 14:46   ` Mika Kuoppala
2014-05-05 12:47 ` [PATCH 05/10] drm/i915/chv: Streamline CHV forcewake stuff deepak.s
2014-05-05 12:47 ` [PATCH 06/10] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-05 12:47 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-05 12:47 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-05 12:47 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-05-05 12:47 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request for CHV deepak.s
2014-05-07 14:23   ` Ville Syrjälä
2014-05-12 13:53   ` deepak.s [this message]
2014-05-15 21:22 ` [PATCH 00/10] Enable RC6/Turbo on CHV Daniel Vetter

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