From: Tom Lendacky <thomas.lendacky@amd.com>
To: <qemu-devel@nongnu.org>, <kvm@vger.kernel.org>
Cc: "Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Michael Roth" <michael.roth@amd.com>
Subject: [PATCH 2/4] qemu-options.hx: Update the reduced-phys-bits documentation
Date: Fri, 30 Sep 2022 10:14:28 -0500 [thread overview]
Message-ID: <13a62ced1808546c1d398e2025cf85f4c94ae123.1664550870.git.thomas.lendacky@amd.com> (raw)
In-Reply-To: <cover.1664550870.git.thomas.lendacky@amd.com>
A guest only ever experiences, at most, 1 bit of reduced physical
addressing. Update the documentation to reflect this as well as change
the example value on the reduced-phys-bits option.
Fixes: a9b4942f48 ("target/i386: add Secure Encrypted Virtualization (SEV) object")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
qemu-options.hx | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 913c71e38f..3396085cf0 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -5391,7 +5391,7 @@ SRST
physical address space. The ``reduced-phys-bits`` is used to
provide the number of bits we loose in physical address space.
Similar to C-bit, the value is Host family dependent. On EPYC,
- the value should be 5.
+ a guest will lose a maximum of 1 bit, so the value should be 1.
The ``sev-device`` provides the device file to use for
communicating with the SEV firmware running inside AMD Secure
@@ -5426,7 +5426,7 @@ SRST
# |qemu_system_x86| \\
...... \\
- -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=5 \\
+ -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=1 \\
-machine ...,memory-encryption=sev0 \\
.....
--
2.37.3
next prev parent reply other threads:[~2022-09-30 15:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 15:14 [PATCH 0/4] Qemu SEV reduced-phys-bits fixes Tom Lendacky
2022-09-30 15:14 ` [PATCH 1/4] qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 Tom Lendacky
2022-10-13 13:22 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` Tom Lendacky [this message]
2022-10-13 13:29 ` [PATCH 2/4] qemu-options.hx: Update the reduced-phys-bits documentation Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 3/4] i386/sev: Update checks and information related to reduced-phys-bits Tom Lendacky
2022-10-13 13:31 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 4/4] i386/cpu: Update how the EBX register of CPUID 0x8000001F is set Tom Lendacky
2022-10-13 14:01 ` Dr. David Alan Gilbert
2023-01-04 18:13 ` [PATCH 0/4] Qemu SEV reduced-phys-bits fixes Tom Lendacky
2023-01-09 15:05 ` Daniel P. Berrangé
2023-04-21 8:48 ` Paolo Bonzini
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