From: "Michel Dänzer" <michel@daenzer.net>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH v2 2/2] drm/radeon: Remove radeon_kms_pflip_irq_get/put() and the pflip atomic
Date: Wed, 2 Jul 2014 12:55:27 +0900 [thread overview]
Message-ID: <1404273327-4465-2-git-send-email-michel@daenzer.net> (raw)
In-Reply-To: <1404273327-4465-1-git-send-email-michel@daenzer.net>
From: Michel Dänzer <michel.daenzer@amd.com>
The vertical blank interrupt is already enabled/disabled via
drm_vblank_get/put(), and radeon_crtc_handle_flip() now bails gracefully
when there is no page flip ready.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
v2: Remove the pflip atomic as well
drivers/gpu/drm/radeon/cik.c | 36 ++++++++--------------
drivers/gpu/drm/radeon/evergreen.c | 36 ++++++++--------------
drivers/gpu/drm/radeon/r100.c | 12 +++-----
drivers/gpu/drm/radeon/r600.c | 12 +++-----
drivers/gpu/drm/radeon/radeon.h | 3 --
drivers/gpu/drm/radeon/radeon_display.c | 5 ---
drivers/gpu/drm/radeon/radeon_irq_kms.c | 54 ---------------------------------
drivers/gpu/drm/radeon/rs600.c | 12 +++-----
drivers/gpu/drm/radeon/si.c | 36 ++++++++--------------
9 files changed, 48 insertions(+), 158 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index d0a994c..43ac3cb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7053,33 +7053,27 @@ int cik_irq_set(struct radeon_device *rdev)
dma_cntl1 |= TRAP_ENABLE;
}
- if (rdev->irq.crtc_vblank_int[0] ||
- atomic_read(&rdev->irq.pflip[0])) {
+ if (rdev->irq.crtc_vblank_int[0]) {
DRM_DEBUG("cik_irq_set: vblank 0\n");
crtc1 |= VBLANK_INTERRUPT_MASK;
}
- if (rdev->irq.crtc_vblank_int[1] ||
- atomic_read(&rdev->irq.pflip[1])) {
+ if (rdev->irq.crtc_vblank_int[1]) {
DRM_DEBUG("cik_irq_set: vblank 1\n");
crtc2 |= VBLANK_INTERRUPT_MASK;
}
- if (rdev->irq.crtc_vblank_int[2] ||
- atomic_read(&rdev->irq.pflip[2])) {
+ if (rdev->irq.crtc_vblank_int[2]) {
DRM_DEBUG("cik_irq_set: vblank 2\n");
crtc3 |= VBLANK_INTERRUPT_MASK;
}
- if (rdev->irq.crtc_vblank_int[3] ||
- atomic_read(&rdev->irq.pflip[3])) {
+ if (rdev->irq.crtc_vblank_int[3]) {
DRM_DEBUG("cik_irq_set: vblank 3\n");
crtc4 |= VBLANK_INTERRUPT_MASK;
}
- if (rdev->irq.crtc_vblank_int[4] ||
- atomic_read(&rdev->irq.pflip[4])) {
+ if (rdev->irq.crtc_vblank_int[4]) {
DRM_DEBUG("cik_irq_set: vblank 4\n");
crtc5 |= VBLANK_INTERRUPT_MASK;
}
- if (rdev->irq.crtc_vblank_int[5] ||
- atomic_read(&rdev->irq.pflip[5])) {
+ if (rdev->irq.crtc_vblank_int[5]) {
DRM_DEBUG("cik_irq_set: vblank 5\n");
crtc6 |= VBLANK_INTERRUPT_MASK;
}
@@ -7421,8 +7415,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[0]))
- radeon_crtc_handle_flip(rdev, 0);
+ radeon_crtc_handle_flip(rdev, 0);
rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
}
@@ -7447,8 +7440,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[1]))
- radeon_crtc_handle_flip(rdev, 1);
+ radeon_crtc_handle_flip(rdev, 1);
rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
}
@@ -7473,8 +7465,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[2]))
- radeon_crtc_handle_flip(rdev, 2);
+ radeon_crtc_handle_flip(rdev, 2);
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
}
@@ -7499,8 +7490,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[3]))
- radeon_crtc_handle_flip(rdev, 3);
+ radeon_crtc_handle_flip(rdev, 3);
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
}
@@ -7525,8 +7515,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[4]))
- radeon_crtc_handle_flip(rdev, 4);
+ radeon_crtc_handle_flip(rdev, 4);
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
}
@@ -7551,8 +7540,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[5]))
- radeon_crtc_handle_flip(rdev, 5);
+ radeon_crtc_handle_flip(rdev, 5);
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
}
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e7d685a..9233dbf 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4411,33 +4411,27 @@ int evergreen_irq_set(struct radeon_device *rdev)
thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
}
- if (rdev->irq.crtc_vblank_int[0] ||
- atomic_read(&rdev->irq.pflip[0])) {
+ if (rdev->irq.crtc_vblank_int[0]) {
DRM_DEBUG("evergreen_irq_set: vblank 0\n");
crtc1 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[1] ||
- atomic_read(&rdev->irq.pflip[1])) {
+ if (rdev->irq.crtc_vblank_int[1]) {
DRM_DEBUG("evergreen_irq_set: vblank 1\n");
crtc2 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[2] ||
- atomic_read(&rdev->irq.pflip[2])) {
+ if (rdev->irq.crtc_vblank_int[2]) {
DRM_DEBUG("evergreen_irq_set: vblank 2\n");
crtc3 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[3] ||
- atomic_read(&rdev->irq.pflip[3])) {
+ if (rdev->irq.crtc_vblank_int[3]) {
DRM_DEBUG("evergreen_irq_set: vblank 3\n");
crtc4 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[4] ||
- atomic_read(&rdev->irq.pflip[4])) {
+ if (rdev->irq.crtc_vblank_int[4]) {
DRM_DEBUG("evergreen_irq_set: vblank 4\n");
crtc5 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[5] ||
- atomic_read(&rdev->irq.pflip[5])) {
+ if (rdev->irq.crtc_vblank_int[5]) {
DRM_DEBUG("evergreen_irq_set: vblank 5\n");
crtc6 |= VBLANK_INT_MASK;
}
@@ -4742,8 +4736,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[0]))
- radeon_crtc_handle_flip(rdev, 0);
+ radeon_crtc_handle_flip(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
}
@@ -4768,8 +4761,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[1]))
- radeon_crtc_handle_flip(rdev, 1);
+ radeon_crtc_handle_flip(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
}
@@ -4794,8 +4786,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[2]))
- radeon_crtc_handle_flip(rdev, 2);
+ radeon_crtc_handle_flip(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
}
@@ -4820,8 +4811,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[3]))
- radeon_crtc_handle_flip(rdev, 3);
+ radeon_crtc_handle_flip(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
}
@@ -4846,8 +4836,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[4]))
- radeon_crtc_handle_flip(rdev, 4);
+ radeon_crtc_handle_flip(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
}
@@ -4872,8 +4861,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[5]))
- radeon_crtc_handle_flip(rdev, 5);
+ radeon_crtc_handle_flip(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
}
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 1f2a960..8fd7294 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -687,12 +687,10 @@ int r100_irq_set(struct radeon_device *rdev)
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
tmp |= RADEON_SW_INT_ENABLE;
}
- if (rdev->irq.crtc_vblank_int[0] ||
- atomic_read(&rdev->irq.pflip[0])) {
+ if (rdev->irq.crtc_vblank_int[0]) {
tmp |= RADEON_CRTC_VBLANK_MASK;
}
- if (rdev->irq.crtc_vblank_int[1] ||
- atomic_read(&rdev->irq.pflip[1])) {
+ if (rdev->irq.crtc_vblank_int[1]) {
tmp |= RADEON_CRTC2_VBLANK_MASK;
}
if (rdev->irq.hpd[0]) {
@@ -753,8 +751,7 @@ int r100_irq_process(struct radeon_device *rdev)
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[0]))
- radeon_crtc_handle_flip(rdev, 0);
+ radeon_crtc_handle_flip(rdev, 0);
}
if (status & RADEON_CRTC2_VBLANK_STAT) {
if (rdev->irq.crtc_vblank_int[1]) {
@@ -762,8 +759,7 @@ int r100_irq_process(struct radeon_device *rdev)
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[1]))
- radeon_crtc_handle_flip(rdev, 1);
+ radeon_crtc_handle_flip(rdev, 1);
}
if (status & RADEON_FP_DETECT_STAT) {
queue_hotplug = true;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 8f318ec..02deff37 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3568,13 +3568,11 @@ int r600_irq_set(struct radeon_device *rdev)
dma_cntl |= TRAP_ENABLE;
}
- if (rdev->irq.crtc_vblank_int[0] ||
- atomic_read(&rdev->irq.pflip[0])) {
+ if (rdev->irq.crtc_vblank_int[0]) {
DRM_DEBUG("r600_irq_set: vblank 0\n");
mode_int |= D1MODE_VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[1] ||
- atomic_read(&rdev->irq.pflip[1])) {
+ if (rdev->irq.crtc_vblank_int[1]) {
DRM_DEBUG("r600_irq_set: vblank 1\n");
mode_int |= D2MODE_VBLANK_INT_MASK;
}
@@ -3869,8 +3867,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[0]))
- radeon_crtc_handle_flip(rdev, 0);
+ radeon_crtc_handle_flip(rdev, 0);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
}
@@ -3895,8 +3892,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[1]))
- radeon_crtc_handle_flip(rdev, 1);
+ radeon_crtc_handle_flip(rdev, 1);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
}
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 7a45c93..a1416f3 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -757,7 +757,6 @@ struct radeon_irq {
spinlock_t lock;
atomic_t ring_int[RADEON_NUM_RINGS];
bool crtc_vblank_int[RADEON_MAX_CRTCS];
- atomic_t pflip[RADEON_MAX_CRTCS];
wait_queue_head_t vblank_queue;
bool hpd[RADEON_MAX_HPD_PINS];
bool afmt[RADEON_MAX_AFMT_BLOCKS];
@@ -769,8 +768,6 @@ int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
-void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
-void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 103d0c6..2742edd 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -325,7 +325,6 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
radeon_fence_unref(&work->fence);
- radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
queue_work(radeon_crtc->flip_queue, &work->unpin_work);
}
@@ -434,10 +433,6 @@ static void radeon_flip_work_func(struct work_struct *__work)
/* We borrow the event spin lock for protecting flip_work */
spin_lock_irqsave(&crtc->dev->event_lock, flags);
-
- /* set the proper interrupt */
- radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
-
work->base = base;
radeon_crtc->flip_status = RADEON_FLIP_READY;
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 089c9ff..5c1caec 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -127,7 +127,6 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
rdev->irq.hpd[i] = false;
for (i = 0; i < RADEON_MAX_CRTCS; i++) {
rdev->irq.crtc_vblank_int[i] = false;
- atomic_set(&rdev->irq.pflip[i], 0);
rdev->irq.afmt[i] = false;
}
radeon_irq_set(rdev);
@@ -175,7 +174,6 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
rdev->irq.hpd[i] = false;
for (i = 0; i < RADEON_MAX_CRTCS; i++) {
rdev->irq.crtc_vblank_int[i] = false;
- atomic_set(&rdev->irq.pflip[i], 0);
rdev->irq.afmt[i] = false;
}
radeon_irq_set(rdev);
@@ -366,58 +364,6 @@ void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
}
/**
- * radeon_irq_kms_pflip_irq_get - enable pageflip interrupt
- *
- * @rdev: radeon device pointer
- * @crtc: crtc whose interrupt you want to enable
- *
- * Enables the pageflip interrupt for a specific crtc (all asics).
- * For pageflips we use the vblank interrupt source.
- */
-void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
-{
- unsigned long irqflags;
-
- if (crtc < 0 || crtc >= rdev->num_crtc)
- return;
-
- if (!rdev->ddev->irq_enabled)
- return;
-
- if (atomic_inc_return(&rdev->irq.pflip[crtc]) == 1) {
- spin_lock_irqsave(&rdev->irq.lock, irqflags);
- radeon_irq_set(rdev);
- spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
- }
-}
-
-/**
- * radeon_irq_kms_pflip_irq_put - disable pageflip interrupt
- *
- * @rdev: radeon device pointer
- * @crtc: crtc whose interrupt you want to disable
- *
- * Disables the pageflip interrupt for a specific crtc (all asics).
- * For pageflips we use the vblank interrupt source.
- */
-void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
-{
- unsigned long irqflags;
-
- if (crtc < 0 || crtc >= rdev->num_crtc)
- return;
-
- if (!rdev->ddev->irq_enabled)
- return;
-
- if (atomic_dec_and_test(&rdev->irq.pflip[crtc])) {
- spin_lock_irqsave(&rdev->irq.lock, irqflags);
- radeon_irq_set(rdev);
- spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
- }
-}
-
-/**
* radeon_irq_kms_enable_afmt - enable audio format change interrupt
*
* @rdev: radeon device pointer
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index b5e63a7..62b044a 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -664,12 +664,10 @@ int rs600_irq_set(struct radeon_device *rdev)
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
tmp |= S_000040_SW_INT_EN(1);
}
- if (rdev->irq.crtc_vblank_int[0] ||
- atomic_read(&rdev->irq.pflip[0])) {
+ if (rdev->irq.crtc_vblank_int[0]) {
mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
}
- if (rdev->irq.crtc_vblank_int[1] ||
- atomic_read(&rdev->irq.pflip[1])) {
+ if (rdev->irq.crtc_vblank_int[1]) {
mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
}
if (rdev->irq.hpd[0]) {
@@ -775,8 +773,7 @@ int rs600_irq_process(struct radeon_device *rdev)
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[0]))
- radeon_crtc_handle_flip(rdev, 0);
+ radeon_crtc_handle_flip(rdev, 0);
}
if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
if (rdev->irq.crtc_vblank_int[1]) {
@@ -784,8 +781,7 @@ int rs600_irq_process(struct radeon_device *rdev)
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[1]))
- radeon_crtc_handle_flip(rdev, 1);
+ radeon_crtc_handle_flip(rdev, 1);
}
if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
queue_hotplug = true;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index fee797f..3dce9f9 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5835,33 +5835,27 @@ int si_irq_set(struct radeon_device *rdev)
DRM_DEBUG("si_irq_set: sw int dma1\n");
dma_cntl1 |= TRAP_ENABLE;
}
- if (rdev->irq.crtc_vblank_int[0] ||
- atomic_read(&rdev->irq.pflip[0])) {
+ if (rdev->irq.crtc_vblank_int[0]) {
DRM_DEBUG("si_irq_set: vblank 0\n");
crtc1 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[1] ||
- atomic_read(&rdev->irq.pflip[1])) {
+ if (rdev->irq.crtc_vblank_int[1]) {
DRM_DEBUG("si_irq_set: vblank 1\n");
crtc2 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[2] ||
- atomic_read(&rdev->irq.pflip[2])) {
+ if (rdev->irq.crtc_vblank_int[2]) {
DRM_DEBUG("si_irq_set: vblank 2\n");
crtc3 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[3] ||
- atomic_read(&rdev->irq.pflip[3])) {
+ if (rdev->irq.crtc_vblank_int[3]) {
DRM_DEBUG("si_irq_set: vblank 3\n");
crtc4 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[4] ||
- atomic_read(&rdev->irq.pflip[4])) {
+ if (rdev->irq.crtc_vblank_int[4]) {
DRM_DEBUG("si_irq_set: vblank 4\n");
crtc5 |= VBLANK_INT_MASK;
}
- if (rdev->irq.crtc_vblank_int[5] ||
- atomic_read(&rdev->irq.pflip[5])) {
+ if (rdev->irq.crtc_vblank_int[5]) {
DRM_DEBUG("si_irq_set: vblank 5\n");
crtc6 |= VBLANK_INT_MASK;
}
@@ -6119,8 +6113,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[0]))
- radeon_crtc_handle_flip(rdev, 0);
+ radeon_crtc_handle_flip(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
}
@@ -6145,8 +6138,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[1]))
- radeon_crtc_handle_flip(rdev, 1);
+ radeon_crtc_handle_flip(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
}
@@ -6171,8 +6163,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[2]))
- radeon_crtc_handle_flip(rdev, 2);
+ radeon_crtc_handle_flip(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
}
@@ -6197,8 +6188,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[3]))
- radeon_crtc_handle_flip(rdev, 3);
+ radeon_crtc_handle_flip(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
}
@@ -6223,8 +6213,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[4]))
- radeon_crtc_handle_flip(rdev, 4);
+ radeon_crtc_handle_flip(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
}
@@ -6249,8 +6238,7 @@ restart_ih:
rdev->pm.vblank_sync = true;
wake_up(&rdev->irq.vblank_queue);
}
- if (atomic_read(&rdev->irq.pflip[5]))
- radeon_crtc_handle_flip(rdev, 5);
+ radeon_crtc_handle_flip(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
}
--
2.0.0
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next prev parent reply other threads:[~2014-07-02 3:55 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-26 9:29 [PATCH 1/2] drm/radeon: Only enable and handle pageflip interrupts when needed Michel Dänzer
2014-06-26 9:29 ` [PATCH 2/2] drm/radeon: Track the status of a page flip more explicitly Michel Dänzer
2014-06-30 9:12 ` [PATCH v2] " Michel Dänzer
2014-06-30 9:14 ` Christian König
2014-07-01 16:23 ` Alex Deucher
2014-06-26 10:39 ` [PATCH 1/2] drm/radeon: Only enable and handle pageflip interrupts when needed Christian König
2014-06-26 11:51 ` Dieter Nützel
2014-06-27 0:53 ` Dieter Nützel
2014-06-27 1:03 ` Michel Dänzer
2014-06-27 1:08 ` Dieter Nützel
2014-06-27 2:06 ` Dieter Nützel
2014-06-27 3:03 ` Michel Dänzer
2014-06-27 3:17 ` Michel Dänzer
2014-06-27 2:58 ` Michel Dänzer
2014-06-27 8:18 ` Christian König
2014-06-27 9:44 ` Michel Dänzer
2014-06-27 10:47 ` Christian König
2014-06-30 9:34 ` Michel Dänzer
2014-06-30 12:31 ` Christian König
2014-06-30 16:22 ` Dieter Nützel
2014-07-01 8:14 ` [PATCH 1/2] drm/radeon: Program page flips to execute in hblank instead of vblank Michel Dänzer
2014-07-01 8:14 ` [PATCH 2/2] drm/radeon: Remove radeon_kms_pflip_irq_get/put() Michel Dänzer
2014-07-01 10:12 ` [PATCH 1/2] drm/radeon: Program page flips to execute in hblank instead of vblank Christian König
2014-07-02 3:55 ` [PATCH v2 " Michel Dänzer
2014-07-02 3:55 ` Michel Dänzer [this message]
2014-07-02 10:10 ` [PATCH 1/2] drm/radeon: Move pinning the BO back to radeon_crtc_page_flip() Michel Dänzer
2014-07-02 10:10 ` [PATCH 2/2] drm/radeon: Complete page flip even if waiting on the BO fence fails Michel Dänzer
2014-07-02 11:42 ` [PATCH 1/2] drm/radeon: Move pinning the BO back to radeon_crtc_page_flip() Christian König
2014-07-02 11:35 ` [PATCH v2 1/2] drm/radeon: Program page flips to execute in hblank instead of vblank Christian König
2014-07-01 16:46 ` [PATCH " Dieter Nützel
2014-07-02 0:29 ` Michel Dänzer
2014-07-02 3:01 ` Dieter Nützel
2014-07-02 3:11 ` Michel Dänzer
2014-07-02 3:52 ` Michel Dänzer
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