All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kishon Vijay Abraham I <kishon@ti.com>
To: <linux-kernel@vger.kernel.org>, <tony@atomide.com>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-omap@vger.kernel.org>
Cc: <kishon@ti.com>, Rajendra Nayak <rnayak@ti.com>,
	Tero Kristo <t-kristo@ti.com>, Paul Walmsley <paul@pwsan.com>,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Kumar Gala <galak@codeaurora.org>
Subject: [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Date: Mon, 14 Jul 2014 16:12:18 +0530	[thread overview]
Message-ID: <1405334543-25509-4-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com>

Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index f5dca1f..3ff6d7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
 		reg = <0x021c>, <0x0220>;
 	};
 
+	optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		#clock-cells = <0>;
+		reg = <0x13b0>;
+		ti,bit-shift = <8>;
+	};
+
 	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
 		compatible = "ti,divider-clock";
 		clocks = <&apll_pcie_ck>;
-- 
1.7.9.5


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: linux-kernel@vger.kernel.org, tony@atomide.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-omap@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
	Paul Walmsley <paul@pwsan.com>, Pawel Moll <pawel.moll@arm.com>,
	Rajendra Nayak <rnayak@ti.com>,
	kishon@ti.com, Tero Kristo <t-kristo@ti.com>,
	Rob Herring <robh+dt@kernel.org>,
	Kumar Gala <galak@codeaurora.org>
Subject: [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Date: Mon, 14 Jul 2014 16:12:18 +0530	[thread overview]
Message-ID: <1405334543-25509-4-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com>

Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index f5dca1f..3ff6d7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
 		reg = <0x021c>, <0x0220>;
 	};
 
+	optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		#clock-cells = <0>;
+		reg = <0x13b0>;
+		ti,bit-shift = <8>;
+	};
+
 	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
 		compatible = "ti,divider-clock";
 		clocks = <&apll_pcie_ck>;
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: kishon@ti.com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Date: Mon, 14 Jul 2014 16:12:18 +0530	[thread overview]
Message-ID: <1405334543-25509-4-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com>

Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index f5dca1f..3ff6d7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
 		reg = <0x021c>, <0x0220>;
 	};
 
+	optfclk_pciephy_32khz: optfclk_pciephy_32khz at 4a0093b0 {
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		#clock-cells = <0>;
+		reg = <0x13b0>;
+		ti,bit-shift = <8>;
+	};
+
 	optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
 		compatible = "ti,divider-clock";
 		clocks = <&apll_pcie_ck>;
-- 
1.7.9.5

  parent reply	other threads:[~2014-07-14 10:44 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 1/8] ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 2/8] ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` Kishon Vijay Abraham I [this message]
2014-07-14 10:42   ` [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 4/8] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 5/8] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe " Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 6/8] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 7/8] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 8/8] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-14 10:42   ` Kishon Vijay Abraham I
2014-07-15  7:18 ` [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Tony Lindgren
2014-07-15  7:18   ` Tony Lindgren
2014-07-15  7:18   ` Tony Lindgren
2014-07-16  4:46   ` Kishon Vijay Abraham I
2014-07-16  4:46     ` Kishon Vijay Abraham I
2014-07-16  4:46     ` Kishon Vijay Abraham I

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1405334543-25509-4-git-send-email-kishon@ti.com \
    --to=kishon@ti.com \
    --cc=devicetree@vger.kernel.org \
    --cc=galak@codeaurora.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-omap@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=paul@pwsan.com \
    --cc=pawel.moll@arm.com \
    --cc=rnayak@ti.com \
    --cc=robh+dt@kernel.org \
    --cc=t-kristo@ti.com \
    --cc=tony@atomide.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.