From: Olav Haugan <ohaugan@codeaurora.org> To: will.deacon@arm.com Cc: mitchelh@codeaurora.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Olav Haugan <ohaugan@codeaurora.org> Subject: [PATCH v2 2/2] iommu/arm-smmu: Do not access non-existing SMR registers Date: Mon, 4 Aug 2014 11:01:03 -0700 [thread overview] Message-ID: <1407175263-10699-3-git-send-email-ohaugan@codeaurora.org> (raw) In-Reply-To: <1407175263-10699-1-git-send-email-ohaugan@codeaurora.org> The SMR registers do not exist when stream matching is not supported by the hardware. Avoid writing to this register if not needed. Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> --- drivers/iommu/arm-smmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c16431f..1f3a5b3 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1731,7 +1731,10 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Mark all SMRn as invalid and all S2CRn as bypass */ for (i = 0; i < smmu->num_mapping_groups; ++i) { - writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); + if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) { + writel_relaxed(~SMR_VALID, + gr0_base + ARM_SMMU_GR0_SMR(i)); + } writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); } -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: ohaugan@codeaurora.org (Olav Haugan) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] iommu/arm-smmu: Do not access non-existing SMR registers Date: Mon, 4 Aug 2014 11:01:03 -0700 [thread overview] Message-ID: <1407175263-10699-3-git-send-email-ohaugan@codeaurora.org> (raw) In-Reply-To: <1407175263-10699-1-git-send-email-ohaugan@codeaurora.org> The SMR registers do not exist when stream matching is not supported by the hardware. Avoid writing to this register if not needed. Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> --- drivers/iommu/arm-smmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c16431f..1f3a5b3 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1731,7 +1731,10 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Mark all SMRn as invalid and all S2CRn as bypass */ for (i = 0; i < smmu->num_mapping_groups; ++i) { - writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); + if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) { + writel_relaxed(~SMR_VALID, + gr0_base + ARM_SMMU_GR0_SMR(i)); + } writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); } -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2014-08-04 18:01 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-08-04 18:01 [PATCH v2 0/2] arm-smmu fixes for CBn_TCR and S2CR/SMR programming Olav Haugan 2014-08-04 18:01 ` Olav Haugan 2014-08-04 18:01 ` [PATCH v2 1/2] iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1 Olav Haugan 2014-08-04 18:01 ` Olav Haugan 2014-08-04 18:01 ` Olav Haugan [this message] 2014-08-04 18:01 ` [PATCH v2 2/2] iommu/arm-smmu: Do not access non-existing SMR registers Olav Haugan 2014-08-06 10:19 ` Will Deacon 2014-08-06 10:19 ` Will Deacon 2014-08-06 16:44 ` Olav Haugan 2014-08-06 16:44 ` Olav Haugan [not found] ` <53E25B76.6090208-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2014-08-06 17:35 ` Will Deacon 2014-08-06 17:35 ` Will Deacon [not found] ` <20140806173518.GG25953-5wv7dgnIgG8@public.gmane.org> 2014-08-06 23:34 ` Olav Haugan 2014-08-06 23:34 ` Olav Haugan 2014-08-07 9:22 ` Will Deacon 2014-08-07 9:22 ` Will Deacon [not found] ` <20140807092254.GH13703-5wv7dgnIgG8@public.gmane.org> 2014-08-08 18:51 ` Olav Haugan 2014-08-08 18:51 ` Olav Haugan
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