From: Bard Liao <bardliao@realtek.com>
To: broonie@kernel.org, lgirdwood@gmail.com
Cc: oder_chiou@realtek.com, Bard Liao <bardliao@realtek.com>,
alsa-devel@alsa-project.org, lars@metafoo.de, flove@realtek.com
Subject: [PATCH 2/2] ASoC: rt286: Fix sync function
Date: Fri, 26 Sep 2014 11:06:40 +0800 [thread overview]
Message-ID: <1411700800-1082-2-git-send-email-bardliao@realtek.com> (raw)
In-Reply-To: <1411700800-1082-1-git-send-email-bardliao@realtek.com>
We try to write index registers into cache when we write an index
register, but we change the reg value before updating the cache.
As a result, the cache is never be updated. This patch will fix
this issue.
Signed-off-by: Bard Liao <bardliao@realtek.com>
---
sound/soc/codecs/rt286.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/rt286.c b/sound/soc/codecs/rt286.c
index 7a66084..b86b426 100644
--- a/sound/soc/codecs/rt286.c
+++ b/sound/soc/codecs/rt286.c
@@ -191,7 +191,6 @@ static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
/*handle index registers*/
if (reg <= 0xff) {
rt286_hw_write(client, RT286_COEF_INDEX, reg);
- reg = RT286_PROC_COEF;
for (i = 0; i < INDEX_CACHE_SIZE; i++) {
if (reg == rt286->index_cache[i].reg) {
rt286->index_cache[i].def = value;
@@ -199,6 +198,7 @@ static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
}
}
+ reg = RT286_PROC_COEF;
}
data[0] = (reg >> 24) & 0xff;
--
1.8.1.1.439.g50a6b54
next prev parent reply other threads:[~2014-09-26 3:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-26 3:06 [PATCH 1/2] ASoC: rt286: Correct default value Bard Liao
2014-09-26 3:06 ` Bard Liao [this message]
2014-09-26 8:14 ` Mark Brown
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