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From: Kever Yang <kever.yang@rock-chips.com>
To: heiko@sntech.de, Mike Turquette <mturquette@linaro.org>
Cc: dianders@chromium.org, sonnyrao@chromium.org,
	addy.ke@rock-chips.com, cf@rock-chips.com, xjq@rock-chips.com,
	hj@rock-chips.com, huangtao@rock-chips.com, dkl@rock-chips.com,
	Kever Yang <kever.yang@rock-chips.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
Date: Tue,  7 Oct 2014 17:33:57 +0800	[thread overview]
Message-ID: <1412674438-26160-2-git-send-email-kever.yang@rock-chips.com> (raw)
In-Reply-To: <1412674438-26160-1-git-send-email-kever.yang@rock-chips.com>

This patch add 400MHz and 500MHz to clock rate table for rk3288.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3288.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index d053529..f6ea9c6 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -86,8 +86,10 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
 	RK3066_PLL_RATE( 594000000, 2, 198, 4),
 	RK3066_PLL_RATE( 552000000, 1, 46, 2),
 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
+	RK3066_PLL_RATE( 500000000, 3, 125, 2),
 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
+	RK3066_PLL_RATE( 400000000, 3, 50, 1),
 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
-- 
1.9.1


WARNING: multiple messages have this Message-ID (diff)
From: kever.yang@rock-chips.com (Kever Yang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
Date: Tue,  7 Oct 2014 17:33:57 +0800	[thread overview]
Message-ID: <1412674438-26160-2-git-send-email-kever.yang@rock-chips.com> (raw)
In-Reply-To: <1412674438-26160-1-git-send-email-kever.yang@rock-chips.com>

This patch add 400MHz and 500MHz to clock rate table for rk3288.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3288.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index d053529..f6ea9c6 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -86,8 +86,10 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
 	RK3066_PLL_RATE( 594000000, 2, 198, 4),
 	RK3066_PLL_RATE( 552000000, 1, 46, 2),
 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
+	RK3066_PLL_RATE( 500000000, 3, 125, 2),
 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
+	RK3066_PLL_RATE( 400000000, 3, 50, 1),
 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
-- 
1.9.1

  reply	other threads:[~2014-10-07  9:36 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-07  9:33 [PATCH 0/2] init some clock rate from dts for rk3288 Kever Yang
2014-10-07  9:33 ` Kever Yang
2014-10-07  9:33 ` Kever Yang
2014-10-07  9:33 ` Kever Yang [this message]
2014-10-07  9:33   ` [PATCH 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate Kever Yang
2014-10-07 16:56   ` Doug Anderson
2014-10-07 16:56     ` Doug Anderson
2014-10-07  9:33 ` [PATCH 2/2] ARM: dts: enable init rate for clock Kever Yang
2014-10-07  9:33   ` Kever Yang
2014-10-07 17:03   ` Doug Anderson
2014-10-07 17:03     ` Doug Anderson
2014-10-07 18:27     ` Heiko Stübner
2014-10-07 18:27       ` Heiko Stübner
2014-10-07 19:20       ` Doug Anderson
2014-10-07 19:20         ` Doug Anderson
2014-10-07 19:20         ` Doug Anderson
2014-10-07 19:37         ` Heiko Stübner
2014-10-07 19:37           ` Heiko Stübner
2014-10-07 19:37           ` Heiko Stübner
2014-10-07 21:10           ` Doug Anderson
2014-10-07 21:10             ` Doug Anderson
2014-10-07 21:10             ` Doug Anderson
2014-10-07 17:11 ` [PATCH 0/2] init some clock rate from dts for rk3288 Doug Anderson
2014-10-07 17:11   ` Doug Anderson

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