From: zyw@rock-chips.com To: Heiko Stuebner <heiko@sntech.de> Cc: Mike Turquette <mturquette@linaro.org>, Ian Campbell <ijc+devicetree@hellion.org.uk>, dianders@chromium.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kumar Gala <galak@codeaurora.org>, Russell King <linux@arm.linux.org.uk>, linux-rockchip@lists.infradead.org, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Chris Zhong <zyw@rock-chips.com>, Mark Rutland <mark.rutland@arm.com>, linux-arm-kernel@lists.infradead.org, Tony Xie <xxx@rock-chips.com> Subject: [PATCH v2 1/4] clk: rockchip: RK3288: add suspend and resume Date: Fri, 17 Oct 2014 13:45:51 -0700 [thread overview] Message-ID: <1413578751-26183-1-git-send-email-zyw@rock-chips.com> (raw) In-Reply-To: <1413578696-26125-1-git-send-email-zyw@rock-chips.com> From: Chris Zhong <zyw@rock-chips.com> save and restore some clks, which might be changed in suspend. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- Changes in v2: - __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed drivers/clk/rockchip/clk-rk3288.c | 63 +++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index b22a2d2..415b928 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -16,6 +16,7 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/syscore_ops.h> #include <dt-bindings/clock/rk3288-cru.h> #include "clk.h" @@ -680,6 +681,67 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), }; +#ifdef CONFIG_PM_SLEEP +static void __iomem *rk3288_cru_base; +static const int rk3288_saved_cru_reg_ids[] = { + RK3288_MODE_CON, + RK3288_CLKSEL_CON(0), + RK3288_CLKSEL_CON(1), + RK3288_CLKSEL_CON(10), + RK3288_CLKSEL_CON(33), + RK3288_CLKSEL_CON(37), +}; + +static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; + +/* + * cru will be set in maskrom when system wake up from fastboot + * mode in suspend, + * so the operation is saving the changed regs. + * The apll/cpll/gpll will be set into slow mode in maskrom. + * It is mean that resume code run in 24m quit slowly! + * so we must resume these plls as soon as possible. + */ +static int rk3288_clk_suspend(void) +{ + int i, reg_id; + + for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) { + reg_id = rk3288_saved_cru_reg_ids[i]; + + rk3288_saved_cru_regs[i] = + readl_relaxed(rk3288_cru_base + reg_id); + } + return 0; +} + +static void rk3288_clk_resume(void) +{ + int i, reg_id; + + for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) { + reg_id = rk3288_saved_cru_reg_ids[i]; + + writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000, + rk3288_cru_base + reg_id); + } +} + +static struct syscore_ops rk3288_clk_syscore_ops = { + .suspend = rk3288_clk_suspend, + .resume = rk3288_clk_resume, +}; + +static void rk3288_clk_sleep_init(void __iomem *reg_base) +{ + rk3288_cru_base = reg_base; + register_syscore_ops(&rk3288_clk_syscore_ops); +} + +#else /* CONFIG_PM_SLEEP */ +static void rk3288_clk_sleep_init(void __iomem *reg_base) {} +#endif + static void __init rk3288_clk_init(struct device_node *np) { void __iomem *reg_base; @@ -713,5 +775,6 @@ static void __init rk3288_clk_init(struct device_node *np) rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); + rk3288_clk_sleep_init(reg_base); } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: zyw@rock-chips.com (zyw at rock-chips.com) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/4] clk: rockchip: RK3288: add suspend and resume Date: Fri, 17 Oct 2014 13:45:51 -0700 [thread overview] Message-ID: <1413578751-26183-1-git-send-email-zyw@rock-chips.com> (raw) In-Reply-To: <1413578696-26125-1-git-send-email-zyw@rock-chips.com> From: Chris Zhong <zyw@rock-chips.com> save and restore some clks, which might be changed in suspend. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- Changes in v2: - __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed drivers/clk/rockchip/clk-rk3288.c | 63 +++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index b22a2d2..415b928 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -16,6 +16,7 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/syscore_ops.h> #include <dt-bindings/clock/rk3288-cru.h> #include "clk.h" @@ -680,6 +681,67 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), }; +#ifdef CONFIG_PM_SLEEP +static void __iomem *rk3288_cru_base; +static const int rk3288_saved_cru_reg_ids[] = { + RK3288_MODE_CON, + RK3288_CLKSEL_CON(0), + RK3288_CLKSEL_CON(1), + RK3288_CLKSEL_CON(10), + RK3288_CLKSEL_CON(33), + RK3288_CLKSEL_CON(37), +}; + +static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; + +/* + * cru will be set in maskrom when system wake up from fastboot + * mode in suspend, + * so the operation is saving the changed regs. + * The apll/cpll/gpll will be set into slow mode in maskrom. + * It is mean that resume code run in 24m quit slowly! + * so we must resume these plls as soon as possible. + */ +static int rk3288_clk_suspend(void) +{ + int i, reg_id; + + for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) { + reg_id = rk3288_saved_cru_reg_ids[i]; + + rk3288_saved_cru_regs[i] = + readl_relaxed(rk3288_cru_base + reg_id); + } + return 0; +} + +static void rk3288_clk_resume(void) +{ + int i, reg_id; + + for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) { + reg_id = rk3288_saved_cru_reg_ids[i]; + + writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000, + rk3288_cru_base + reg_id); + } +} + +static struct syscore_ops rk3288_clk_syscore_ops = { + .suspend = rk3288_clk_suspend, + .resume = rk3288_clk_resume, +}; + +static void rk3288_clk_sleep_init(void __iomem *reg_base) +{ + rk3288_cru_base = reg_base; + register_syscore_ops(&rk3288_clk_syscore_ops); +} + +#else /* CONFIG_PM_SLEEP */ +static void rk3288_clk_sleep_init(void __iomem *reg_base) {} +#endif + static void __init rk3288_clk_init(struct device_node *np) { void __iomem *reg_base; @@ -713,5 +775,6 @@ static void __init rk3288_clk_init(struct device_node *np) rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); + rk3288_clk_sleep_init(reg_base); } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); -- 1.7.9.5
next prev parent reply other threads:[~2014-10-17 20:46 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-10-17 20:44 [PATCH v2 0/4] add suspend support for RK3288 zyw 2014-10-17 20:44 ` zyw at rock-chips.com 2014-10-17 20:44 ` zyw-TNX95d0MmH7DzftRWevZcw 2014-10-17 20:45 ` zyw [this message] 2014-10-17 20:45 ` [PATCH v2 1/4] clk: rockchip: RK3288: add suspend and resume zyw at rock-chips.com 2014-10-17 20:47 ` [PATCH v2 2/4] ARM: rockchip: add suspend and resume for RK3288 zyw 2014-10-17 20:47 ` zyw at rock-chips.com 2014-10-17 20:47 ` zyw 2014-10-18 0:57 ` Doug Anderson 2014-10-18 0:57 ` Doug Anderson 2014-10-18 0:57 ` Doug Anderson 2014-10-17 20:47 ` [PATCH v2 3/4] ARM: rockchip: Add pmu-sram binding zyw 2014-10-17 20:47 ` zyw at rock-chips.com 2014-10-17 20:47 ` [PATCH v2 4/4] ARM: dts: add RK3288 suspend support zyw 2014-10-17 20:47 ` zyw at rock-chips.com
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