From: Kever Yang <kever.yang@rock-chips.com> To: Mike Turquette <mturquette@linaro.org>, Heiko Stuebner <heiko@sntech.de> Cc: dianders@chromium.org, sonnyrao@chromium.org, addy.ke@rock-chips.com, cf@rock-chips.com, fzf@rock-chips.com, ykk@rock-chips.com, yzq@rock-chips.com, dkl@rock-chips.com, huangtao@rock-chips.com, Kever Yang <kever.yang@rock-chips.com>, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] clk: rockchip: introduce the div_ops handling for composite branches Date: Tue, 4 Nov 2014 15:52:37 +0800 [thread overview] Message-ID: <1415087559-19444-4-git-send-email-kever.yang@rock-chips.com> (raw) In-Reply-To: <1415087559-19444-1-git-send-email-kever.yang@rock-chips.com> Rockchip Socs have a lot of clock node registered as composite branch which include mux, divider and gate, most of them use the same ops handling callback, we still need special ops handling for some special clock node and this patch make it possible. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- drivers/clk/rockchip/clk.c | 13 +++++++++---- drivers/clk/rockchip/clk.h | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 1e68bff..0917c2b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -42,6 +42,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, + const struct clk_ops *divops, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) @@ -90,9 +91,12 @@ static struct clk *rockchip_clk_register_branch(const char *name, div->width = div_width; div->lock = lock; div->table = div_table; - div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) - ? &clk_divider_ro_ops - : &clk_divider_ops; + if (divops) + div_ops = divops; + else if (div_flags & CLK_DIVIDER_READ_ONLY) + div_ops = &clk_divider_ro_ops; + else + div_ops = &clk_divider_ops; } clk = clk_register_composite(NULL, name, parent_names, num_parents, @@ -275,7 +279,8 @@ void __init rockchip_clk_register_branches( reg_base, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, list->div_shift, list->div_width, - list->div_flags, list->div_table, + list->div_flags, + list->div_ops, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 6baf665..2cf263b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -185,6 +185,7 @@ struct rockchip_clk_branch { u8 div_shift; u8 div_width; u8 div_flags; + const struct clk_ops *div_ops; struct clk_div_table *div_table; int gate_offset; u8 gate_shift; @@ -212,6 +213,29 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_DIVOPS(_id, cname, pnames, f, mo, ms, mw, mf, \ + ds, dw, df, dops, go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .div_ops = dops, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + + #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ go, gs, gf) \ { \ -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: kever.yang@rock-chips.com (Kever Yang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/5] clk: rockchip: introduce the div_ops handling for composite branches Date: Tue, 4 Nov 2014 15:52:37 +0800 [thread overview] Message-ID: <1415087559-19444-4-git-send-email-kever.yang@rock-chips.com> (raw) In-Reply-To: <1415087559-19444-1-git-send-email-kever.yang@rock-chips.com> Rockchip Socs have a lot of clock node registered as composite branch which include mux, divider and gate, most of them use the same ops handling callback, we still need special ops handling for some special clock node and this patch make it possible. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- drivers/clk/rockchip/clk.c | 13 +++++++++---- drivers/clk/rockchip/clk.h | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 1e68bff..0917c2b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -42,6 +42,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, + const struct clk_ops *divops, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) @@ -90,9 +91,12 @@ static struct clk *rockchip_clk_register_branch(const char *name, div->width = div_width; div->lock = lock; div->table = div_table; - div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) - ? &clk_divider_ro_ops - : &clk_divider_ops; + if (divops) + div_ops = divops; + else if (div_flags & CLK_DIVIDER_READ_ONLY) + div_ops = &clk_divider_ro_ops; + else + div_ops = &clk_divider_ops; } clk = clk_register_composite(NULL, name, parent_names, num_parents, @@ -275,7 +279,8 @@ void __init rockchip_clk_register_branches( reg_base, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, list->div_shift, list->div_width, - list->div_flags, list->div_table, + list->div_flags, + list->div_ops, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 6baf665..2cf263b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -185,6 +185,7 @@ struct rockchip_clk_branch { u8 div_shift; u8 div_width; u8 div_flags; + const struct clk_ops *div_ops; struct clk_div_table *div_table; int gate_offset; u8 gate_shift; @@ -212,6 +213,29 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_DIVOPS(_id, cname, pnames, f, mo, ms, mw, mf, \ + ds, dw, df, dops, go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .div_ops = dops, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + + #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ go, gs, gf) \ { \ -- 1.9.1
next prev parent reply other threads:[~2014-11-04 7:55 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-11-04 7:52 [PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288 Kever Yang 2014-11-04 7:52 ` Kever Yang 2014-11-04 7:52 ` [PATCH 1/5] clk: rockchip: add some clock rate into rate table for rk3288 Kever Yang 2014-11-04 7:52 ` Kever Yang 2014-11-04 7:52 ` [PATCH 2/5] clk: divider: make clk_divider_recalc/set_rate available Kever Yang 2014-11-04 7:52 ` Kever Yang [this message] 2014-11-04 7:52 ` [PATCH 3/5] clk: rockchip: introduce the div_ops handling for composite branches Kever Yang 2014-11-04 7:52 ` [PATCH 4/5] clk: rockchip: add the vop_determine_rate for vop dclock Kever Yang 2014-11-04 7:52 ` Kever Yang 2014-11-04 7:52 ` [PATCH 5/5] clk: rockchip: change DCLK_VOP0 to use new COMPOSITE_DIVOPS Kever Yang 2014-11-04 7:52 ` Kever Yang 2014-11-06 21:06 ` [PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288 Heiko Stübner 2014-11-06 21:06 ` Heiko Stübner 2014-11-13 8:52 ` Kever Yang 2014-11-13 8:52 ` Kever Yang 2014-11-13 22:59 ` Doug Anderson 2014-11-13 22:59 ` Doug Anderson [not found] ` <20141114014605.25314.49766@quantum> 2014-11-14 8:58 ` Kever Yang 2014-11-14 8:58 ` Kever Yang 2016-01-19 12:02 ` Tomeu Vizoso 2016-01-19 12:02 ` Tomeu Vizoso 2016-01-20 16:50 ` Doug Anderson 2016-01-20 16:50 ` Doug Anderson 2016-01-21 9:03 ` Tomeu Vizoso 2016-01-21 9:03 ` Tomeu Vizoso 2016-01-21 20:11 ` Doug Anderson 2016-01-21 20:11 ` Doug Anderson 2016-01-22 14:00 ` Tomeu Vizoso 2016-01-22 14:00 ` Tomeu Vizoso 2016-01-22 17:07 ` Doug Anderson 2016-01-22 17:07 ` Doug Anderson 2016-01-26 8:28 ` Tomeu Vizoso 2016-01-26 8:28 ` Tomeu Vizoso 2016-01-26 16:32 ` Doug Anderson 2016-01-26 16:32 ` Doug Anderson 2016-01-27 10:20 ` Tomeu Vizoso 2016-01-27 10:20 ` Tomeu Vizoso 2016-01-27 16:46 ` Doug Anderson 2016-01-27 16:46 ` Doug Anderson
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