From: andre.przywara@arm.com (Andre Przywara)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 09/19] arm/arm64: KVM: make the value of ICC_SRE_EL1 a per-VM variable
Date: Mon, 8 Dec 2014 12:37:44 +0000 [thread overview]
Message-ID: <1418042274-3246-10-git-send-email-andre.przywara@arm.com> (raw)
In-Reply-To: <1418042274-3246-1-git-send-email-andre.przywara@arm.com>
ICC_SRE_EL1 is a system register allowing msr/mrs accesses to the
GIC CPU interface for EL1 (guests). Currently we force it to 0, but
for proper GICv3 support we have to allow guests to use it (depending
on their selected virtual GIC model).
So add ICC_SRE_EL1 to the list of saved/restored registers on a
world switch, but actually disallow a guest to change it by only
restoring a fixed, once-initialized value.
This value depends on the GIC model userland has chosen for a guest.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
---
Changelog v4...v5:
(none)
Changelog v3...v4:
- initialize variable on declaration
arch/arm64/kernel/asm-offsets.c | 1 +
arch/arm64/kvm/vgic-v3-switch.S | 14 +++++++++-----
include/kvm/arm_vgic.h | 1 +
virt/kvm/arm/vgic-v3.c | 8 ++++++--
4 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index 9a9fce0..9d34486 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -140,6 +140,7 @@ int main(void)
DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));
DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr));
DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr));
+ DEFINE(VGIC_V3_CPU_SRE, offsetof(struct vgic_cpu, vgic_v3.vgic_sre));
DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr));
DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr));
DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr));
diff --git a/arch/arm64/kvm/vgic-v3-switch.S b/arch/arm64/kvm/vgic-v3-switch.S
index d160469..617a012 100644
--- a/arch/arm64/kvm/vgic-v3-switch.S
+++ b/arch/arm64/kvm/vgic-v3-switch.S
@@ -148,17 +148,18 @@
* x0: Register pointing to VCPU struct
*/
.macro restore_vgic_v3_state
- // Disable SRE_EL1 access. Necessary, otherwise
- // ICH_VMCR_EL2.VFIQEn becomes one, and FIQ happens...
- msr_s ICC_SRE_EL1, xzr
- isb
-
// Compute the address of struct vgic_cpu
add x3, x0, #VCPU_VGIC_CPU
// Restore all interesting registers
ldr w4, [x3, #VGIC_V3_CPU_HCR]
ldr w5, [x3, #VGIC_V3_CPU_VMCR]
+ ldr w25, [x3, #VGIC_V3_CPU_SRE]
+
+ msr_s ICC_SRE_EL1, x25
+
+ // make sure SRE is valid before writing the other registers
+ isb
msr_s ICH_HCR_EL2, x4
msr_s ICH_VMCR_EL2, x5
@@ -244,9 +245,12 @@
dsb sy
// Prevent the guest from touching the GIC system registers
+ // if SRE isn't enabled for GICv3 emulation
+ cbnz x25, 1f
mrs_s x5, ICC_SRE_EL2
and x5, x5, #~ICC_SRE_EL2_ENABLE
msr_s ICC_SRE_EL2, x5
+1:
.endm
ENTRY(__save_vgic_v3_state)
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 72a9fef..f7570f83 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -245,6 +245,7 @@ struct vgic_v3_cpu_if {
#ifdef CONFIG_ARM_GIC_V3
u32 vgic_hcr;
u32 vgic_vmcr;
+ u32 vgic_sre; /* Restored only, change ignored */
u32 vgic_misr; /* Saved only */
u32 vgic_eisr; /* Saved only */
u32 vgic_elrsr; /* Saved only */
diff --git a/virt/kvm/arm/vgic-v3.c b/virt/kvm/arm/vgic-v3.c
index ea39bad..5249048 100644
--- a/virt/kvm/arm/vgic-v3.c
+++ b/virt/kvm/arm/vgic-v3.c
@@ -145,15 +145,19 @@ static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
static void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
+ struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
+
/*
* By forcing VMCR to zero, the GIC will restore the binary
* points to their reset values. Anything else resets to zero
* anyway.
*/
- vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = 0;
+ vgic_v3->vgic_vmcr = 0;
+
+ vgic_v3->vgic_sre = 0;
/* Get the show on the road... */
- vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr = ICH_HCR_EN;
+ vgic_v3->vgic_hcr = ICH_HCR_EN;
}
static const struct vgic_ops vgic_v3_ops = {
--
1.7.9.5
next prev parent reply other threads:[~2014-12-08 12:37 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-08 12:37 [PATCH v5 00/19] KVM GICv3 emulation Andre Przywara
2014-12-08 12:37 ` [PATCH v5 01/19] arm/arm64: KVM: rework MPIDR assignment and add accessors Andre Przywara
2014-12-08 15:06 ` Mark Rutland
2014-12-08 15:26 ` Andre Przywara
2014-12-18 9:00 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 02/19] arm/arm64: KVM: pass down user space provided GIC type into vGIC code Andre Przywara
2014-12-18 9:03 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 03/19] arm/arm64: KVM: refactor vgic_handle_mmio() function Andre Przywara
2014-12-18 9:06 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 04/19] arm/arm64: KVM: wrap 64 bit MMIO accesses with two 32 bit ones Andre Przywara
2014-12-18 9:09 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 05/19] arm/arm64: KVM: introduce per-VM ops Andre Przywara
2014-12-13 13:29 ` Christoffer Dall
2014-12-23 11:43 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 06/19] arm/arm64: KVM: move kvm_register_device_ops() into vGIC probing Andre Przywara
2014-12-23 11:57 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 07/19] arm/arm64: KVM: dont rely on a valid GICH base address Andre Przywara
2014-12-23 11:58 ` Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 08/19] arm/arm64: KVM: make the maximum number of vCPUs a per-VM value Andre Przywara
2014-12-13 13:31 ` Christoffer Dall
2014-12-23 12:07 ` Marc Zyngier
2015-01-05 17:34 ` Andre Przywara
2015-01-06 13:29 ` Christoffer Dall
2015-01-06 14:03 ` Andre Przywara
2015-01-06 13:58 ` Peter Maydell
2014-12-08 12:37 ` Andre Przywara [this message]
2014-12-23 12:14 ` [PATCH v5 09/19] arm/arm64: KVM: make the value of ICC_SRE_EL1 a per-VM variable Marc Zyngier
2014-12-08 12:37 ` [PATCH v5 10/19] arm/arm64: KVM: refactor MMIO accessors Andre Przywara
2014-12-08 12:37 ` [PATCH v5 11/19] arm/arm64: KVM: refactor/wrap vgic_set/get_attr() Andre Przywara
2014-12-08 12:37 ` [PATCH v5 12/19] arm/arm64: KVM: add vgic.h header file Andre Przywara
2014-12-08 12:37 ` [PATCH v5 13/19] arm/arm64: KVM: split GICv2 specific emulation code from vgic.c Andre Przywara
2014-12-08 12:37 ` [PATCH v5 14/19] arm/arm64: KVM: add opaque private pointer to MMIO data Andre Przywara
2014-12-08 12:37 ` [PATCH v5 15/19] arm/arm64: KVM: add virtual GICv3 distributor emulation Andre Przywara
2014-12-13 13:37 ` Christoffer Dall
2014-12-15 11:32 ` Andre Przywara
2014-12-08 12:37 ` [PATCH v5 16/19] arm64: GICv3: introduce symbolic names for GICv3 ICC_SGI1R_EL1 fields Andre Przywara
2014-12-08 12:37 ` [PATCH v5 17/19] arm64: KVM: add SGI generation register emulation Andre Przywara
2014-12-08 12:37 ` [PATCH v5 18/19] arm/arm64: KVM: enable kernel side of GICv3 emulation Andre Przywara
2014-12-13 13:42 ` Christoffer Dall
2015-01-05 17:58 ` Andre Przywara
2014-12-08 12:37 ` [PATCH v5 19/19] arm/arm64: KVM: allow userland to request a virtual GICv3 Andre Przywara
2014-12-13 13:45 ` Christoffer Dall
2014-12-15 11:50 ` Andre Przywara
2014-12-15 13:02 ` Christoffer Dall
2014-12-13 13:53 ` [PATCH v5 00/19] KVM GICv3 emulation Christoffer Dall
2014-12-15 14:57 ` Andre Przywara
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