From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> To: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement <gregory.clement@free-electrons.com>, devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>, Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Tawfik Bayouk <tawfik@marvell.com>, Nadav Haklai <nadavh@marvell.com>, Lior Amsalem <alior@marvell.com>, Ezequiel Garcia <ezequiel.garcia@free-electrons.com>, Maxime Ripard <maxime.ripard@free-electrons.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Subject: [PATCH 05/10] clk: mvebu: extend common code to allow an optional refclk Date: Fri, 6 Feb 2015 16:57:51 +0100 [thread overview] Message-ID: <1423238276-9206-6-git-send-email-thomas.petazzoni@free-electrons.com> (raw) In-Reply-To: <1423238276-9206-1-git-send-email-thomas.petazzoni@free-electrons.com> The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- drivers/clk/mvebu/common.c | 17 +++++++++++++++++ drivers/clk/mvebu/common.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 0d4d121..15b370f 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; + + /* One more clock for the optional refclk */ + if (desc->get_refclk_freq) + clk_data.clk_num += 1; + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np, WARN_ON(IS_ERR(clk_data.clks[2+n])); }; + /* Register optional refclk */ + if (desc->get_refclk_freq) { + const char *name = "refclk"; + of_property_read_string_index(np, "clock-output-names", + 2 + desc->num_ratios, &name); + rate = desc->get_refclk_freq(base); + clk_data.clks[2 + desc->num_ratios] = + clk_register_fixed_rate(NULL, name, NULL, + CLK_IS_ROOT, rate); + WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); + } + /* SAR register isn't needed anymore */ iounmap(base); diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h index 783b563..f0de6c8 100644 --- a/drivers/clk/mvebu/common.h +++ b/drivers/clk/mvebu/common.h @@ -30,6 +30,7 @@ struct coreclk_soc_desc { u32 (*get_tclk_freq)(void __iomem *sar); u32 (*get_cpu_freq)(void __iomem *sar); void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); + u32 (*get_refclk_freq)(void __iomem *sar); bool (*is_sscg_enabled)(void __iomem *sar); u32 (*fix_sscg_deviation)(u32 system_clk); const struct coreclk_ratio *ratios; -- 2.1.0
WARNING: multiple messages have this Message-ID (diff)
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/10] clk: mvebu: extend common code to allow an optional refclk Date: Fri, 6 Feb 2015 16:57:51 +0100 [thread overview] Message-ID: <1423238276-9206-6-git-send-email-thomas.petazzoni@free-electrons.com> (raw) In-Reply-To: <1423238276-9206-1-git-send-email-thomas.petazzoni@free-electrons.com> The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- drivers/clk/mvebu/common.c | 17 +++++++++++++++++ drivers/clk/mvebu/common.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 0d4d121..15b370f 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; + + /* One more clock for the optional refclk */ + if (desc->get_refclk_freq) + clk_data.clk_num += 1; + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np, WARN_ON(IS_ERR(clk_data.clks[2+n])); }; + /* Register optional refclk */ + if (desc->get_refclk_freq) { + const char *name = "refclk"; + of_property_read_string_index(np, "clock-output-names", + 2 + desc->num_ratios, &name); + rate = desc->get_refclk_freq(base); + clk_data.clks[2 + desc->num_ratios] = + clk_register_fixed_rate(NULL, name, NULL, + CLK_IS_ROOT, rate); + WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); + } + /* SAR register isn't needed anymore */ iounmap(base); diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h index 783b563..f0de6c8 100644 --- a/drivers/clk/mvebu/common.h +++ b/drivers/clk/mvebu/common.h @@ -30,6 +30,7 @@ struct coreclk_soc_desc { u32 (*get_tclk_freq)(void __iomem *sar); u32 (*get_cpu_freq)(void __iomem *sar); void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); + u32 (*get_refclk_freq)(void __iomem *sar); bool (*is_sscg_enabled)(void __iomem *sar); u32 (*fix_sscg_deviation)(u32 system_clk); const struct coreclk_ratio *ratios; -- 2.1.0
next prev parent reply other threads:[~2015-02-06 15:58 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-02-06 15:57 [PATCH 00/10] ARM: mvebu: add basic support for Armada 39x Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 01/10] devicetree: bindings: add DT binding for the Marvell Armada 39x SoC family Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 02/10] devicetree: bindings: update DT bindings for Marvell EBU clock support Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 03/10] devicetree: bindings: add Device Tree bindings for Armada 39x pin-muxing controller Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 17:05 ` Andrew Lunn 2015-02-06 17:05 ` Andrew Lunn 2015-02-20 11:11 ` Thomas Petazzoni 2015-02-20 11:11 ` Thomas Petazzoni [not found] ` <20150220121134.25cb865c-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2015-02-20 14:18 ` Andrew Lunn 2015-02-20 14:18 ` Andrew Lunn 2015-02-06 15:57 ` Thomas Petazzoni [this message] 2015-02-06 15:57 ` [PATCH 05/10] clk: mvebu: extend common code to allow an optional refclk Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 06/10] clk: mvebu: add Marvell Armada 39x driver Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 07/10] pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-03-04 12:54 ` Linus Walleij 2015-03-04 12:54 ` Linus Walleij 2015-03-04 13:05 ` Thomas Petazzoni 2015-03-04 13:05 ` Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 08/10] ARM: mvebu: add core support for " Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 19:57 ` Stephen Boyd 2015-02-06 19:57 ` Stephen Boyd 2015-02-20 13:05 ` Thomas Petazzoni 2015-02-20 13:05 ` Thomas Petazzoni [not found] ` <1423238276-9206-9-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2015-02-06 20:31 ` Maxime Ripard 2015-02-06 20:31 ` Maxime Ripard [not found] ` <1423238276-9206-1-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2015-02-06 15:57 ` [PATCH 04/10] devicetree: bindings: add new SMP enable method for Marvell " Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 15:57 ` [PATCH 09/10] ARM: mvebu: add Device Tree files for Armada 39x SoC and board Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni 2015-02-06 17:21 ` Andrew Lunn 2015-02-06 17:21 ` Andrew Lunn 2015-02-20 14:14 ` Thomas Petazzoni 2015-02-20 14:14 ` Thomas Petazzoni 2015-02-20 14:45 ` Andrew Lunn 2015-02-20 14:45 ` Andrew Lunn 2015-02-20 15:46 ` Thomas Petazzoni 2015-02-20 15:46 ` Thomas Petazzoni 2015-02-06 20:39 ` Maxime Ripard 2015-02-06 20:39 ` Maxime Ripard 2015-02-06 15:57 ` [PATCH 10/10] Documentation: arm: update supported Marvell EBU processors Thomas Petazzoni 2015-02-06 15:57 ` Thomas Petazzoni
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