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From: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
To: <ath10k@lists.infradead.org>
Cc: <linux-wireless@vger.kernel.org>,
	Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
Subject: [PATCH v2 1/2] ath10k: Bypass PLL setting on target init for QCA9888
Date: Mon, 9 Feb 2015 11:16:53 +0530	[thread overview]
Message-ID: <1423460814-2767-1-git-send-email-rmanohar@qti.qualcomm.com> (raw)

Some of of qca988x solutions are having global reset issue
during target initialization. Bypassing PLL setting before
downloading firmware and letting the SoC run on REF_CLK is fixing
the problem. Corresponding firmware change is also needed to set
the clock source once the target is initialized. Since 10.2.4
firmware is having this ROM patch, applying skip_clock_init only
for 10.2.4 firmware versions.

Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
---
 drivers/net/wireless/ath/ath10k/core.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index 310e12b..cd20805 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -797,6 +797,16 @@ static int ath10k_download_cal_data(struct ath10k *ar)
 	ar->cal_mode = ATH10K_CAL_MODE_OTP;
 
 done:
+	if ((ar->hw_rev == ATH10K_HW_QCA988X) &&
+	    (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_10_2_4)) {
+		ret = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
+		if (ret) {
+			ath10k_err(ar, "could not write skip_clock_init (%d)\n",
+				   ret);
+			return ret;
+		}
+	}
+
 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
 		   ath10k_cal_mode_str(ar->cal_mode));
 	return 0;
-- 
2.2.2


WARNING: multiple messages have this Message-ID (diff)
From: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
To: ath10k@lists.infradead.org
Cc: linux-wireless@vger.kernel.org,
	Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
Subject: [PATCH v2 1/2] ath10k: Bypass PLL setting on target init for QCA9888
Date: Mon, 9 Feb 2015 11:16:53 +0530	[thread overview]
Message-ID: <1423460814-2767-1-git-send-email-rmanohar@qti.qualcomm.com> (raw)

Some of of qca988x solutions are having global reset issue
during target initialization. Bypassing PLL setting before
downloading firmware and letting the SoC run on REF_CLK is fixing
the problem. Corresponding firmware change is also needed to set
the clock source once the target is initialized. Since 10.2.4
firmware is having this ROM patch, applying skip_clock_init only
for 10.2.4 firmware versions.

Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
---
 drivers/net/wireless/ath/ath10k/core.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index 310e12b..cd20805 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -797,6 +797,16 @@ static int ath10k_download_cal_data(struct ath10k *ar)
 	ar->cal_mode = ATH10K_CAL_MODE_OTP;
 
 done:
+	if ((ar->hw_rev == ATH10K_HW_QCA988X) &&
+	    (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_10_2_4)) {
+		ret = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
+		if (ret) {
+			ath10k_err(ar, "could not write skip_clock_init (%d)\n",
+				   ret);
+			return ret;
+		}
+	}
+
 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
 		   ath10k_cal_mode_str(ar->cal_mode));
 	return 0;
-- 
2.2.2


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             reply	other threads:[~2015-02-09  5:47 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-09  5:46 Rajkumar Manoharan [this message]
2015-02-09  5:46 ` [PATCH v2 1/2] ath10k: Bypass PLL setting on target init for QCA9888 Rajkumar Manoharan
2015-02-09  5:46 ` [PATCH v2 2/2] ath10k: Increase copy engine entries for rx wmi Rajkumar Manoharan
2015-02-09  5:46   ` Rajkumar Manoharan
2015-02-09 22:54   ` Peter Oh
2015-02-09 22:54     ` Peter Oh
2015-02-10  7:26     ` Rajkumar
2015-02-10  7:26       ` Rajkumar
2015-03-05 13:53   ` Kalle Valo
2015-03-05 13:53     ` Kalle Valo
2015-02-17  7:11 ` [PATCH v2 1/2] ath10k: Bypass PLL setting on target init for QCA9888 Rajkumar
2015-02-17  7:11   ` Rajkumar
2015-03-05 12:41 ` Kalle Valo
2015-03-05 12:41   ` Kalle Valo
2015-03-15  8:06   ` Rajkumar Manoharan
2015-03-15  8:06     ` Rajkumar Manoharan

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