From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhang.chunyan@linaro.org, kaixu.xia@linaro.org Subject: [PATCH 5/5] coresight-stm: Bindings for System Trace Macrocell Date: Fri, 27 Feb 2015 16:04:54 -0700 [thread overview] Message-ID: <1425078294-13059-6-git-send-email-mathieu.poirier@linaro.org> (raw) In-Reply-To: <1425078294-13059-1-git-send-email-mathieu.poirier@linaro.org> The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6..648d50024429 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -31,6 +32,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -198,3 +207,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name. -- 1.9.1
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From: mathieu.poirier@linaro.org (Mathieu Poirier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] coresight-stm: Bindings for System Trace Macrocell Date: Fri, 27 Feb 2015 16:04:54 -0700 [thread overview] Message-ID: <1425078294-13059-6-git-send-email-mathieu.poirier@linaro.org> (raw) In-Reply-To: <1425078294-13059-1-git-send-email-mathieu.poirier@linaro.org> The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6..648d50024429 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -31,6 +32,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -198,3 +207,22 @@ Example: }; }; }; + +4. STM + stm at 20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name. -- 1.9.1
next prev parent reply other threads:[~2015-02-27 23:05 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-02-27 23:04 [PATCH 0/5] coresight: next Mathieu Poirier 2015-02-27 23:04 ` Mathieu Poirier 2015-02-27 23:04 ` [PATCH 1/5] coresight: making cpu index lookup arm64 compliant Mathieu Poirier 2015-02-27 23:04 ` Mathieu Poirier 2015-02-27 23:04 ` [PATCH 2/5] coresight: fixing compilation warnings picked up by 64bit compiler Mathieu Poirier 2015-02-27 23:04 ` Mathieu Poirier 2015-02-27 23:04 ` [PATCH 3/5] coresight: Adding coresight support for arm64 architecture Mathieu Poirier 2015-02-27 23:04 ` Mathieu Poirier 2015-02-27 23:04 ` [PATCH 4/5] coresight-stm: adding driver for CoreSight STM component Mathieu Poirier 2015-02-27 23:04 ` Mathieu Poirier 2015-03-07 12:27 ` Alexander Shishkin 2015-03-07 12:27 ` Alexander Shishkin 2015-03-30 14:04 ` Alexander Shishkin 2015-03-30 14:04 ` Alexander Shishkin 2015-03-30 15:48 ` Mathieu Poirier 2015-03-30 15:48 ` Mathieu Poirier 2015-03-31 15:04 ` Alexander Shishkin 2015-03-31 15:04 ` Alexander Shishkin 2015-04-01 14:27 ` Mathieu Poirier 2015-04-01 14:27 ` Mathieu Poirier 2015-04-01 14:28 ` Mathieu Poirier 2015-04-01 14:28 ` Mathieu Poirier 2015-02-27 23:04 ` Mathieu Poirier [this message] 2015-02-27 23:04 ` [PATCH 5/5] coresight-stm: Bindings for System Trace Macrocell Mathieu Poirier 2015-03-19 22:09 ` [PATCH 0/5] coresight: next Mathieu Poirier 2015-03-19 22:09 ` Mathieu Poirier 2015-03-19 22:24 ` Greg KH 2015-03-19 22:24 ` Greg KH
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