From: Aaron Brice <aaron.brice@datasoft.com> To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, stefan@agner.ch, devicetree@vger.kernel.org Subject: [PATCH v3 2/3] devicetree: spi: fsl-dspi: Add cs-sck delays Date: Fri, 3 Apr 2015 13:39:30 -0700 [thread overview] Message-ID: <1428093571-20407-3-git-send-email-aaron.brice@datasoft.com> (raw) In-Reply-To: <1428093571-20407-1-git-send-email-aaron.brice@datasoft.com> Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to support delays before and after starting the clock in a transfer. Signed-off-by: Aaron Brice <aaron.brice@datasoft.com> --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index cbbe16e..70af78a 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -16,6 +16,12 @@ Optional property: in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. +Optional SPI slave node properties: +- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip + select and the start of clock signal, at the start of a transfer. +- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock + signal and deactivating chip select, at the end of a transfer. + Example: dspi0@4002c000 { @@ -43,6 +49,8 @@ dspi0@4002c000 { reg = <0>; linux,modalias = "m25p80"; modal = "at26df081a"; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; }; }; -- 2.1.0
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From: Aaron Brice <aaron.brice-vSOi0k5x9wFWk0Htik3J/w@public.gmane.org> To: broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, stefan-XLVq0VzYD2Y@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH v3 2/3] devicetree: spi: fsl-dspi: Add cs-sck delays Date: Fri, 3 Apr 2015 13:39:30 -0700 [thread overview] Message-ID: <1428093571-20407-3-git-send-email-aaron.brice@datasoft.com> (raw) In-Reply-To: <1428093571-20407-1-git-send-email-aaron.brice-vSOi0k5x9wFWk0Htik3J/w@public.gmane.org> Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to support delays before and after starting the clock in a transfer. Signed-off-by: Aaron Brice <aaron.brice-vSOi0k5x9wFWk0Htik3J/w@public.gmane.org> --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index cbbe16e..70af78a 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -16,6 +16,12 @@ Optional property: in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. +Optional SPI slave node properties: +- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip + select and the start of clock signal, at the start of a transfer. +- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock + signal and deactivating chip select, at the end of a transfer. + Example: dspi0@4002c000 { @@ -43,6 +49,8 @@ dspi0@4002c000 { reg = <0>; linux,modalias = "m25p80"; modal = "at26df081a"; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; }; }; -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2015-04-03 20:39 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-04-03 20:39 [PATCH v3 0/3] spi: fsl-dspi (vf610) clock fixes Aaron Brice 2015-04-03 20:39 ` Aaron Brice 2015-04-03 20:39 ` [PATCH v3 1/3] spi: fsl-dspi: Fix clock rate scale values Aaron Brice 2015-04-03 20:39 ` Aaron Brice 2015-04-06 17:11 ` Mark Brown 2015-04-06 17:11 ` Mark Brown 2015-04-03 20:39 ` Aaron Brice [this message] 2015-04-03 20:39 ` [PATCH v3 2/3] devicetree: spi: fsl-dspi: Add cs-sck delays Aaron Brice 2015-04-06 17:12 ` Mark Brown 2015-04-06 17:12 ` Mark Brown 2015-04-03 20:39 ` [PATCH v3 3/3] spi: fsl-dspi: Add ~50ns delay between cs and sck Aaron Brice 2015-04-06 17:12 ` Mark Brown 2015-04-06 17:12 ` Mark Brown
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