From: Vignesh R <vigneshr@ti.com>
To: Paul Walmsley <paul@pwsan.com>, Tero Kristo <t-kristo@ti.com>,
Thierry Reding <thierry.reding@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Benoit Cousson <bcousson@baylibre.com>,
Tony Lindgren <tony@atomide.com>,
Russell King <linux@arm.linux.org.uk>,
Mike Turquette <mturquette@linaro.org>,
Stephen Boyd <sboyd@codeaurora.org>
Cc: <linux-pwm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>, Vignesh R <vigneshr@ti.com>
Subject: [PATCH 5/5] ARM: dts: DRA7: Add dt nodes for PWMSS
Date: Mon, 1 Jun 2015 17:23:34 +0530 [thread overview]
Message-ID: <1433159614-437-6-git-send-email-vigneshr@ti.com> (raw)
In-Reply-To: <1433159614-437-1-git-send-email-vigneshr@ti.com>
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 8 +++
.../devicetree/bindings/pwm/pwm-tipwmss.txt | 17 +++++-
arch/arm/boot/dts/dra7.dtsi | 64 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 9c100b2c5b23..25d91ae57de5 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
for am33xx - compatible = "ti,am33xx-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
@@ -27,3 +28,10 @@ ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
};
+
+ehrpwm0: ehrpwm@0 { /* EHRPWM on dra7xx */
+ compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ ti,hwmods = "ehrpwm0";
+};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
index f7eae77f8354..9270ce6b2da2 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
@@ -1,7 +1,9 @@
TI SOC based PWM Subsystem
Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
+- compatible: Must be "ti,<soc>-pwmss".
+ for am33xx - compatible = "ti,am33xx-pwmss"
+ for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"
- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
Should set to 1.
@@ -29,3 +31,16 @@ pwmss0: pwmss@48300000 {
/* child nodes go here */
};
+
+epwmss0: epwmss@4843e000 { /* On DRA7xx */
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */
+ 0x4843e180 0x4843e180 0x80 /* EQEP */
+ 0x4843e200 0x4843e200 0x80>; /* EHRPWM */
+
+ /* child nodes go here */
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 387c76ca41f9..98a9203d6992 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1474,6 +1474,70 @@
clocks = <&sys_clkin1>;
status = "disabled";
};
+
+ epwmss0: epwmss@4843e000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */
+ 0x4843e180 0x4843e180 0x80 /* EQEP */
+ 0x4843e200 0x4843e200 0x80>;/* EHRPWM */
+
+ ehrpwm0: ehrpwm@4843e200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ ti,hwmods = "ehrpwm0";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss@48440000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48440100 0x48440100 0x80 /* ECAP */
+ 0x48440180 0x48440180 0x80 /* EQEP */
+ 0x48440200 0x48440200 0x80>; /* EHRPWM */
+
+ ehrpwm1: ehrpwm@48440200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ ti,hwmods = "ehrpwm1";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss@48442000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ ranges = <0x48442100 0x48442100 0x80 /* ECAP */
+ 0x48442180 0x48442180 0x80 /* EQEP */
+ 0x48442200 0x48442200 0x80>; /* EHRPWM */
+
+ ehrpwm2: ehrpwm@48442200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ ti,hwmods = "ehrpwm2";
+ status = "disabled";
+ };
+ };
};
thermal_zones: thermal-zones {
--
2.4.1
WARNING: multiple messages have this Message-ID (diff)
From: Vignesh R <vigneshr@ti.com>
To: Paul Walmsley <paul@pwsan.com>, Tero Kristo <t-kristo@ti.com>,
Thierry Reding <thierry.reding@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Benoit Cousson <bcousson@baylibre.com>,
Tony Lindgren <tony@atomide.com>,
Russell King <linux@arm.linux.org.uk>,
Mike Turquette <mturquette@linaro.org>,
Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Vignesh R <vigneshr@ti.com>
Subject: [PATCH 5/5] ARM: dts: DRA7: Add dt nodes for PWMSS
Date: Mon, 1 Jun 2015 17:23:34 +0530 [thread overview]
Message-ID: <1433159614-437-6-git-send-email-vigneshr@ti.com> (raw)
In-Reply-To: <1433159614-437-1-git-send-email-vigneshr@ti.com>
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 8 +++
.../devicetree/bindings/pwm/pwm-tipwmss.txt | 17 +++++-
arch/arm/boot/dts/dra7.dtsi | 64 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 9c100b2c5b23..25d91ae57de5 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
for am33xx - compatible = "ti,am33xx-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
@@ -27,3 +28,10 @@ ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
};
+
+ehrpwm0: ehrpwm@0 { /* EHRPWM on dra7xx */
+ compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ ti,hwmods = "ehrpwm0";
+};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
index f7eae77f8354..9270ce6b2da2 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
@@ -1,7 +1,9 @@
TI SOC based PWM Subsystem
Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
+- compatible: Must be "ti,<soc>-pwmss".
+ for am33xx - compatible = "ti,am33xx-pwmss"
+ for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"
- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
Should set to 1.
@@ -29,3 +31,16 @@ pwmss0: pwmss@48300000 {
/* child nodes go here */
};
+
+epwmss0: epwmss@4843e000 { /* On DRA7xx */
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */
+ 0x4843e180 0x4843e180 0x80 /* EQEP */
+ 0x4843e200 0x4843e200 0x80>; /* EHRPWM */
+
+ /* child nodes go here */
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 387c76ca41f9..98a9203d6992 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1474,6 +1474,70 @@
clocks = <&sys_clkin1>;
status = "disabled";
};
+
+ epwmss0: epwmss@4843e000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */
+ 0x4843e180 0x4843e180 0x80 /* EQEP */
+ 0x4843e200 0x4843e200 0x80>;/* EHRPWM */
+
+ ehrpwm0: ehrpwm@4843e200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ ti,hwmods = "ehrpwm0";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss@48440000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48440100 0x48440100 0x80 /* ECAP */
+ 0x48440180 0x48440180 0x80 /* EQEP */
+ 0x48440200 0x48440200 0x80>; /* EHRPWM */
+
+ ehrpwm1: ehrpwm@48440200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ ti,hwmods = "ehrpwm1";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss@48442000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ ranges = <0x48442100 0x48442100 0x80 /* ECAP */
+ 0x48442180 0x48442180 0x80 /* EQEP */
+ 0x48442200 0x48442200 0x80>; /* EHRPWM */
+
+ ehrpwm2: ehrpwm@48442200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ ti,hwmods = "ehrpwm2";
+ status = "disabled";
+ };
+ };
};
thermal_zones: thermal-zones {
--
2.4.1
WARNING: multiple messages have this Message-ID (diff)
From: vigneshr@ti.com (Vignesh R)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] ARM: dts: DRA7: Add dt nodes for PWMSS
Date: Mon, 1 Jun 2015 17:23:34 +0530 [thread overview]
Message-ID: <1433159614-437-6-git-send-email-vigneshr@ti.com> (raw)
In-Reply-To: <1433159614-437-1-git-send-email-vigneshr@ti.com>
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 8 +++
.../devicetree/bindings/pwm/pwm-tipwmss.txt | 17 +++++-
arch/arm/boot/dts/dra7.dtsi | 64 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 9c100b2c5b23..25d91ae57de5 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
for am33xx - compatible = "ti,am33xx-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
@@ -27,3 +28,10 @@ ehrpwm0: ehrpwm at 0 { /* EHRPWM on da850 */
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
};
+
+ehrpwm0: ehrpwm at 0 { /* EHRPWM on dra7xx */
+ compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ ti,hwmods = "ehrpwm0";
+};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
index f7eae77f8354..9270ce6b2da2 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
@@ -1,7 +1,9 @@
TI SOC based PWM Subsystem
Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
+- compatible: Must be "ti,<soc>-pwmss".
+ for am33xx - compatible = "ti,am33xx-pwmss"
+ for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"
- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
Should set to 1.
@@ -29,3 +31,16 @@ pwmss0: pwmss at 48300000 {
/* child nodes go here */
};
+
+epwmss0: epwmss at 4843e000 { /* On DRA7xx */
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */
+ 0x4843e180 0x4843e180 0x80 /* EQEP */
+ 0x4843e200 0x4843e200 0x80>; /* EHRPWM */
+
+ /* child nodes go here */
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 387c76ca41f9..98a9203d6992 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1474,6 +1474,70 @@
clocks = <&sys_clkin1>;
status = "disabled";
};
+
+ epwmss0: epwmss at 4843e000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */
+ 0x4843e180 0x4843e180 0x80 /* EQEP */
+ 0x4843e200 0x4843e200 0x80>;/* EHRPWM */
+
+ ehrpwm0: ehrpwm at 4843e200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ ti,hwmods = "ehrpwm0";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss at 48440000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48440100 0x48440100 0x80 /* ECAP */
+ 0x48440180 0x48440180 0x80 /* EQEP */
+ 0x48440200 0x48440200 0x80>; /* EHRPWM */
+
+ ehrpwm1: ehrpwm at 48440200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ ti,hwmods = "ehrpwm1";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss at 48442000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ ranges = <0x48442100 0x48442100 0x80 /* ECAP */
+ 0x48442180 0x48442180 0x80 /* EQEP */
+ 0x48442200 0x48442200 0x80>; /* EHRPWM */
+
+ ehrpwm2: ehrpwm at 48442200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ ti,hwmods = "ehrpwm2";
+ status = "disabled";
+ };
+ };
};
thermal_zones: thermal-zones {
--
2.4.1
next prev parent reply other threads:[~2015-06-01 11:56 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-01 11:53 [PATCH 0/5] Add support for PWMSS on DRA7 Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` [PATCH 1/5] ARM: OMAP2+: DRA7: clockdomain: change l4per2_7xx_clkdm to SW_WKUP Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` [PATCH 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-02 8:21 ` Tero Kristo
2015-06-02 8:21 ` Tero Kristo
2015-06-02 8:21 ` Tero Kristo
2015-06-02 11:24 ` Vignesh R
2015-06-02 11:24 ` Vignesh R
2015-06-02 11:24 ` Vignesh R
2015-06-01 11:53 ` [PATCH 3/5] ARM: dts: DRA7: Add TBCLK " Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-02 8:22 ` Tero Kristo
2015-06-02 8:22 ` Tero Kristo
2015-06-02 8:22 ` Tero Kristo
2015-06-02 11:23 ` Vignesh R
2015-06-02 11:23 ` Vignesh R
2015-06-02 11:23 ` Vignesh R
2015-06-01 11:53 ` [PATCH 4/5] clk: ti: DRA7: Add tbclk data for ehrpwm Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` Vignesh R
2015-06-01 11:53 ` Vignesh R [this message]
2015-06-01 11:53 ` [PATCH 5/5] ARM: dts: DRA7: Add dt nodes for PWMSS Vignesh R
2015-06-01 11:53 ` Vignesh R
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