From: Geert Uytterhoeven <geert+renesas@glider.be>
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH/RFC 14/15] ARM: shmobile: r8a7793 dtsi: Add SYSC PM domains
Date: Thu, 04 Jun 2015 18:53:40 +0000 [thread overview]
Message-ID: <1433444021-22167-15-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be>
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7793.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index a7e892fe3efa7fd3..498c9fb389f38fbd 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -30,6 +30,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7793_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ power-domains = <&pd_ca15_cpu0>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@@ -53,6 +54,7 @@
L2_CA15: cache-controller@0 {
compatible = "cache";
+ power-domains = <&pd_ca15_scu>;
arm,data-latency = <4 4 0>;
arm,tag-latency = <3 3 3>;
@@ -396,4 +398,40 @@
};
};
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,sysc-r8a7793", "renesas,sysc-rcar";
+ reg = <0 0xe6180000 0 0x0200>;
+
+ pm-domains {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pd_ca15_scu: scu@12 {
+ reg = <12 0x180>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_ca15_cpu0: cpu@0 {
+ reg = <0 0x40>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_ca15_cpu1: cpu@1 {
+ reg = <1 0x41>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ pd_sh: sh@16 {
+ reg = <16 0x80>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_sgx: sgx@20 {
+ reg = <20 0xc0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
};
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Kevin Hilman <khilman@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
Lina Iyer <lina.iyer@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Pawel Moll <pawel.moll@arm.com>
Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH/RFC 14/15] ARM: shmobile: r8a7793 dtsi: Add SYSC PM domains
Date: Thu, 4 Jun 2015 20:53:40 +0200 [thread overview]
Message-ID: <1433444021-22167-15-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be>
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7793.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index a7e892fe3efa7fd3..498c9fb389f38fbd 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -30,6 +30,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7793_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ power-domains = <&pd_ca15_cpu0>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@@ -53,6 +54,7 @@
L2_CA15: cache-controller@0 {
compatible = "cache";
+ power-domains = <&pd_ca15_scu>;
arm,data-latency = <4 4 0>;
arm,tag-latency = <3 3 3>;
@@ -396,4 +398,40 @@
};
};
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,sysc-r8a7793", "renesas,sysc-rcar";
+ reg = <0 0xe6180000 0 0x0200>;
+
+ pm-domains {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pd_ca15_scu: scu@12 {
+ reg = <12 0x180>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_ca15_cpu0: cpu@0 {
+ reg = <0 0x40>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_ca15_cpu1: cpu@1 {
+ reg = <1 0x41>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ pd_sh: sh@16 {
+ reg = <16 0x80>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_sgx: sgx@20 {
+ reg = <20 0xc0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
};
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: geert+renesas@glider.be (Geert Uytterhoeven)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH/RFC 14/15] ARM: shmobile: r8a7793 dtsi: Add SYSC PM domains
Date: Thu, 4 Jun 2015 20:53:40 +0200 [thread overview]
Message-ID: <1433444021-22167-15-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be>
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7793.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index a7e892fe3efa7fd3..498c9fb389f38fbd 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -30,6 +30,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7793_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ power-domains = <&pd_ca15_cpu0>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@@ -53,6 +54,7 @@
L2_CA15: cache-controller at 0 {
compatible = "cache";
+ power-domains = <&pd_ca15_scu>;
arm,data-latency = <4 4 0>;
arm,tag-latency = <3 3 3>;
@@ -396,4 +398,40 @@
};
};
+ sysc: system-controller at e6180000 {
+ compatible = "renesas,sysc-r8a7793", "renesas,sysc-rcar";
+ reg = <0 0xe6180000 0 0x0200>;
+
+ pm-domains {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pd_ca15_scu: scu at 12 {
+ reg = <12 0x180>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_ca15_cpu0: cpu at 0 {
+ reg = <0 0x40>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_ca15_cpu1: cpu at 1 {
+ reg = <1 0x41>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ pd_sh: sh at 16 {
+ reg = <16 0x80>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_sgx: sgx at 20 {
+ reg = <20 0xc0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
};
--
1.9.1
next prev parent reply other threads:[~2015-06-04 18:53 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-04 18:53 [PATCH/RFC 00/15] ARM: shmobile: R-Car: Add SYSC PM Domain DT Support Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 01/15] PM / Domains: Add DT bindings for the R-Car System Controller Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 02/15] ARM: shmobile: R-Car: Add DT support for PM domains Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-24 12:11 ` Geert Uytterhoeven
2015-06-24 12:11 ` Geert Uytterhoeven
2015-06-24 12:11 ` Geert Uytterhoeven
2015-06-24 12:11 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 03/15] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 04/15] ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 05/15] ARM: shmobile: r8a7793 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 06/15] ARM: shmobile: r8a7794 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 07/15] ARM: shmobile: r8a7790 dtsi: Add L1 cache information to CPU nodes Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 08/15] ARM: shmobile: r8a7791 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 09/15] ARM: shmobile: r8a7793 dtsi: Add L1 cache information to CPU node Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 10/15] ARM: shmobile: r8a7794 dtsi: Add L1 cache information to CPU nodes Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 11/15] ARM: shmobile: r8a7779 dtsi: Add SYSC PM domains Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 12/15] ARM: shmobile: r8a7790 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 13/15] ARM: shmobile: r8a7791 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven [this message]
2015-06-04 18:53 ` [PATCH/RFC 14/15] ARM: shmobile: r8a7793 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 15/15] ARM: shmobile: r8a7794 " Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven
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