From: Caesar Wang <wxt@rock-chips.com> To: Heiko Stuebner <heiko@sntech.de> Cc: dianders@chromium.org, Dmitry Torokhov <dmitry.torokhov@gmail.com>, linux-rockchip@lists.infradead.org, Caesar Wang <wxt@rock-chips.com>, Russell King <linux@arm.linux.org.uk>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] ARM: rockchip: fix the SMP code style Date: Fri, 5 Jun 2015 23:11:44 +0800 [thread overview] Message-ID: <1433517104-7595-4-git-send-email-wxt@rock-chips.com> (raw) In-Reply-To: <1433517104-7595-1-git-send-email-wxt@rock-chips.com> Use the below scripts to check: scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c Although there is a check, it's no matter. CHECK: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt +167udelay(10); total: 0 errors, 0 warnings, 1 checks, 362 lines checked Changes in v3: - FIx the PATCH v2, it doesn't work on chromium 3.14. Changes in v2: - As Kever points out, Fix the subject typo WIF/WFI in PATCH [2/3]. - As Heiko suggestion, re-adjust the cpu on/off flow in PATCH [1/3]. - Use the checkpatch.pl -f --subjective to check in PATCH [3/3]. Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- arch/arm/mach-rockchip/platsmp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 6672fdd..ac9173e 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -113,7 +113,7 @@ static int pmu_set_power_domain(int pd, bool on) ret = pmu_power_domain_is_on(pd); if (ret < 0) { pr_err("%s: could not read power domain state\n", - __func__); + __func__); return ret; } } @@ -137,7 +137,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, if (cpu >= ncores) { pr_err("%s: cpu %d outside maximum number of cpus %d\n", - __func__, cpu, ncores); + __func__, cpu, ncores); return -ENXIO; } @@ -156,7 +156,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, * */ udelay(10); writel(virt_to_phys(rockchip_secondary_startup), - sram_base_addr + 8); + sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); } @@ -335,7 +335,7 @@ static int rockchip_cpu_kill(unsigned int cpu) static void rockchip_cpu_die(unsigned int cpu) { v7_exit_coherency_flush(louis); - while(1) + while (1) cpu_do_idle(); } #endif @@ -348,4 +348,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { .cpu_die = rockchip_cpu_die, #endif }; + CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: wxt@rock-chips.com (Caesar Wang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/3] ARM: rockchip: fix the SMP code style Date: Fri, 5 Jun 2015 23:11:44 +0800 [thread overview] Message-ID: <1433517104-7595-4-git-send-email-wxt@rock-chips.com> (raw) In-Reply-To: <1433517104-7595-1-git-send-email-wxt@rock-chips.com> Use the below scripts to check: scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c Although there is a check, it's no matter. CHECK: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt +167udelay(10); total: 0 errors, 0 warnings, 1 checks, 362 lines checked Changes in v3: - FIx the PATCH v2, it doesn't work on chromium 3.14. Changes in v2: - As Kever points out, Fix the subject typo WIF/WFI in PATCH [2/3]. - As Heiko suggestion, re-adjust the cpu on/off flow in PATCH [1/3]. - Use the checkpatch.pl -f --subjective to check in PATCH [3/3]. Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- arch/arm/mach-rockchip/platsmp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 6672fdd..ac9173e 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -113,7 +113,7 @@ static int pmu_set_power_domain(int pd, bool on) ret = pmu_power_domain_is_on(pd); if (ret < 0) { pr_err("%s: could not read power domain state\n", - __func__); + __func__); return ret; } } @@ -137,7 +137,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, if (cpu >= ncores) { pr_err("%s: cpu %d outside maximum number of cpus %d\n", - __func__, cpu, ncores); + __func__, cpu, ncores); return -ENXIO; } @@ -156,7 +156,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, * */ udelay(10); writel(virt_to_phys(rockchip_secondary_startup), - sram_base_addr + 8); + sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); } @@ -335,7 +335,7 @@ static int rockchip_cpu_kill(unsigned int cpu) static void rockchip_cpu_die(unsigned int cpu) { v7_exit_coherency_flush(louis); - while(1) + while (1) cpu_do_idle(); } #endif @@ -348,4 +348,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { .cpu_die = rockchip_cpu_die, #endif }; + CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); -- 1.9.1
next prev parent reply other threads:[~2015-06-05 15:13 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-05 15:11 [PATCH v3 0/3] ARM: rockchip: fix the SMP Caesar Wang 2015-06-05 15:11 ` Caesar Wang 2015-06-05 15:11 ` [PATCH v3 1/3] ARM: rockchip: fix the CPU soft reset Caesar Wang 2015-06-05 15:11 ` Caesar Wang 2015-06-05 15:52 ` Heiko Stübner 2015-06-05 15:52 ` Heiko Stübner 2015-06-05 15:52 ` Heiko Stübner 2015-06-05 16:17 ` Heiko Stübner 2015-06-05 16:17 ` Heiko Stübner 2015-06-05 16:28 ` Doug Anderson 2015-06-05 16:28 ` Doug Anderson 2015-06-05 16:28 ` Doug Anderson 2015-06-05 15:11 ` [PATCH v3 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state Caesar Wang 2015-06-05 15:11 ` Caesar Wang 2015-06-05 17:49 ` Doug Anderson 2015-06-05 17:49 ` Doug Anderson 2015-06-05 17:49 ` Doug Anderson 2015-06-05 18:29 ` Russell King - ARM Linux 2015-06-05 18:29 ` Russell King - ARM Linux 2015-06-05 18:29 ` Russell King - ARM Linux 2015-06-05 20:24 ` Doug Anderson 2015-06-05 20:24 ` Doug Anderson 2015-06-05 20:24 ` Doug Anderson 2015-06-08 4:56 ` Caesar Wang 2015-06-08 4:56 ` Caesar Wang 2015-06-08 4:56 ` Caesar Wang 2015-06-08 20:52 ` Doug Anderson 2015-06-08 20:52 ` Doug Anderson 2015-06-08 20:52 ` Doug Anderson 2015-06-05 15:11 ` Caesar Wang [this message] 2015-06-05 15:11 ` [PATCH v3 3/3] ARM: rockchip: fix the SMP code style Caesar Wang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1433517104-7595-4-git-send-email-wxt@rock-chips.com \ --to=wxt@rock-chips.com \ --cc=dianders@chromium.org \ --cc=dmitry.torokhov@gmail.com \ --cc=heiko@sntech.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-rockchip@lists.infradead.org \ --cc=linux@arm.linux.org.uk \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.