From: Heiko Stuebner <heiko@sntech.de> To: mturquette@linaro.org, sboyd@codeaurora.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>, stable@vger.kernel.org Subject: [PATCH v2 1/9] clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac Date: Thu, 18 Jun 2015 16:18:28 +0200 [thread overview] Message-ID: <1434637116-17124-2-git-send-email-heiko@sntech.de> (raw) In-Reply-To: <1434637116-17124-1-git-send-email-heiko@sntech.de> The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 4f817ed..0211162 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -578,7 +578,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(2), 5, GFLAGS), - MUX(SCLK_MAC, "mac_clk", mux_mac_p, 0, + MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(21), 4, 1, MFLAGS), GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0, RK3288_CLKGATE_CON(5), 3, GFLAGS), -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/9] clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac Date: Thu, 18 Jun 2015 16:18:28 +0200 [thread overview] Message-ID: <1434637116-17124-2-git-send-email-heiko@sntech.de> (raw) In-Reply-To: <1434637116-17124-1-git-send-email-heiko@sntech.de> The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288") Cc: stable at vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 4f817ed..0211162 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -578,7 +578,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(2), 5, GFLAGS), - MUX(SCLK_MAC, "mac_clk", mux_mac_p, 0, + MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(21), 4, 1, MFLAGS), GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0, RK3288_CLKGATE_CON(5), 3, GFLAGS), -- 2.1.4
next prev parent reply other threads:[~2015-06-18 14:17 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-18 14:18 [PATCH v2 0/9] clk: rockchip: add support for the clock-tree of the rk3368 Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner [this message] 2015-06-18 14:18 ` [PATCH v2 1/9] clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac Heiko Stuebner 2015-07-02 22:51 ` Stephen Boyd 2015-07-02 22:51 ` Stephen Boyd 2015-06-18 14:18 ` [PATCH v2 2/9] clk: rockchip: fix faulty vip parent name on rk3288 Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-07-02 22:51 ` Stephen Boyd 2015-07-02 22:51 ` Stephen Boyd 2015-07-02 22:51 ` Stephen Boyd 2015-06-18 14:18 ` [PATCH v2 3/9] clk: rockchip: protect register macros against multipart values Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-07-02 22:51 ` Stephen Boyd 2015-07-02 22:51 ` Stephen Boyd 2015-07-02 22:51 ` Stephen Boyd 2015-06-18 14:18 ` [PATCH v2 4/9] clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-07-02 22:52 ` Stephen Boyd 2015-07-02 22:52 ` Stephen Boyd 2015-07-02 22:52 ` Stephen Boyd 2015-06-18 14:18 ` [PATCH v2 5/9] clk: rockchip: add support for phase inverters Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-07-02 21:52 ` Stephen Boyd 2015-07-02 21:52 ` Stephen Boyd 2015-07-02 21:52 ` Stephen Boyd 2015-06-18 14:18 ` [PATCH v2 6/9] clk: rockchip: define the inverters of rk3066/rk3188 and rk3288 Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner [not found] ` <1434637116-17124-1-git-send-email-heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> 2015-06-18 14:18 ` [PATCH v2 7/9] dt-bindings: add documentation of rk3668 clock controller Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` [PATCH v2 8/9] clk: rockchip: add dt-binding header for rk3368 Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-07-02 21:54 ` Stephen Boyd 2015-07-02 21:54 ` Stephen Boyd 2015-07-02 21:54 ` Stephen Boyd 2015-06-18 14:18 ` [PATCH v2 9/9] clk: rockchip: add rk3368 clock controller Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner 2015-06-18 14:18 ` Heiko Stuebner
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