From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, christoffer.dall@linaro.org, will.deacon@arm.com, marc.zyngier@arm.com, alex.bennee@linaro.org, shannon.zhao@linaro.org, zhaoshenglong@huawei.com Subject: [PATCH 01/18] ARM64: Move PMU register related defines to asm/pmu.h Date: Mon, 6 Jul 2015 10:17:31 +0800 [thread overview] Message-ID: <1436149068-3784-2-git-send-email-shannon.zhao@linaro.org> (raw) In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> From: Shannon Zhao <shannon.zhao@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> --- arch/arm64/include/asm/pmu.h | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/perf_event.c | 35 -------------------------------- 2 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h index b7710a5..b9f394a 100644 --- a/arch/arm64/include/asm/pmu.h +++ b/arch/arm64/include/asm/pmu.h @@ -19,6 +19,51 @@ #ifndef __ASM_PMU_H #define __ASM_PMU_H +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#define ARMV8_PMCR_N_MASK 0x1f +#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#define ARMV8_CNTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#define ARMV8_INTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ +#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#define ARMV8_EXCLUDE_EL1 (1 << 31) +#define ARMV8_EXCLUDE_EL0 (1 << 30) +#define ARMV8_INCLUDE_EL2 (1 << 27) + #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index fd26e57..0790cac 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -824,9 +824,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_COUNTER0 1 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#define ARMV8_MAX_COUNTERS 32 -#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -837,38 +834,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#define ARMV8_PMCR_N_MASK 0x1f -#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ -#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv3 - */ -#define ARMV8_EXCLUDE_EL1 (1 << 31) -#define ARMV8_EXCLUDE_EL0 (1 << 30) -#define ARMV8_INCLUDE_EL2 (1 << 27) - static inline u32 armv8pmu_pmcr_read(void) { u32 val; -- 2.1.0
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From: shannon.zhao@linaro.org (shannon.zhao at linaro.org) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/18] ARM64: Move PMU register related defines to asm/pmu.h Date: Mon, 6 Jul 2015 10:17:31 +0800 [thread overview] Message-ID: <1436149068-3784-2-git-send-email-shannon.zhao@linaro.org> (raw) In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> From: Shannon Zhao <shannon.zhao@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> --- arch/arm64/include/asm/pmu.h | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/perf_event.c | 35 -------------------------------- 2 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h index b7710a5..b9f394a 100644 --- a/arch/arm64/include/asm/pmu.h +++ b/arch/arm64/include/asm/pmu.h @@ -19,6 +19,51 @@ #ifndef __ASM_PMU_H #define __ASM_PMU_H +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#define ARMV8_PMCR_N_MASK 0x1f +#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#define ARMV8_CNTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#define ARMV8_INTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ +#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#define ARMV8_EXCLUDE_EL1 (1 << 31) +#define ARMV8_EXCLUDE_EL0 (1 << 30) +#define ARMV8_INCLUDE_EL2 (1 << 27) + #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index fd26e57..0790cac 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -824,9 +824,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_COUNTER0 1 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#define ARMV8_MAX_COUNTERS 32 -#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -837,38 +834,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#define ARMV8_PMCR_N_MASK 0x1f -#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ -#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv3 - */ -#define ARMV8_EXCLUDE_EL1 (1 << 31) -#define ARMV8_EXCLUDE_EL0 (1 << 30) -#define ARMV8_INCLUDE_EL2 (1 << 27) - static inline u32 armv8pmu_pmcr_read(void) { u32 val; -- 2.1.0
next prev parent reply other threads:[~2015-07-06 2:17 UTC|newest] Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-07-06 2:17 [PATCH 00/18] KVM: ARM64: Add guest PMU support shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-06 2:17 ` shannon.zhao [this message] 2015-07-06 2:17 ` [PATCH 01/18] ARM64: Move PMU register related defines to asm/pmu.h shannon.zhao at linaro.org 2015-07-08 17:18 ` Will Deacon 2015-07-08 17:18 ` Will Deacon 2015-07-06 2:17 ` [PATCH 02/18] KVM: ARM64: Add initial support for PMU shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-16 18:25 ` Christoffer Dall 2015-07-16 18:25 ` Christoffer Dall 2015-07-17 8:13 ` Shannon Zhao 2015-07-17 8:13 ` Shannon Zhao 2015-07-17 9:58 ` Christoffer Dall 2015-07-17 9:58 ` Christoffer Dall 2015-07-17 11:34 ` Shannon Zhao 2015-07-17 11:34 ` Shannon Zhao 2015-07-17 12:48 ` Christoffer Dall 2015-07-17 12:48 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-16 18:45 ` Christoffer Dall 2015-07-16 18:45 ` Christoffer Dall 2015-07-17 8:25 ` Shannon Zhao 2015-07-17 8:25 ` Shannon Zhao 2015-07-17 10:17 ` Christoffer Dall 2015-07-17 10:17 ` Christoffer Dall 2015-07-17 11:40 ` Shannon Zhao 2015-07-17 11:40 ` Shannon Zhao 2015-07-06 2:17 ` [PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-16 19:55 ` Christoffer Dall 2015-07-16 19:55 ` Christoffer Dall 2015-07-17 8:45 ` Shannon Zhao 2015-07-17 8:45 ` Shannon Zhao 2015-07-17 10:21 ` Christoffer Dall 2015-07-17 10:21 ` Christoffer Dall 2015-07-21 1:16 ` Shannon Zhao 2015-07-21 1:16 ` Shannon Zhao 2015-08-03 19:39 ` Christoffer Dall 2015-08-03 19:39 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 05/18] KVM: ARM64: Add reset and access handlers for PMSELR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-06 2:17 ` [PATCH 06/18] KVM: ARM64: Add reset and access handlers for PMCEID0_EL0 and PMCEID1_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 13:51 ` Christoffer Dall 2015-07-17 13:51 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 07/18] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 14:30 ` Christoffer Dall 2015-07-17 14:30 ` Christoffer Dall 2015-07-21 1:35 ` Shannon Zhao 2015-07-21 1:35 ` Shannon Zhao 2015-08-03 19:55 ` Christoffer Dall 2015-08-03 19:55 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 08/18] KVM: ARM64: Add reset and access handlers for PMXEVTYPER_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-06 2:17 ` [PATCH 09/18] KVM: ARM64: Add reset and access handlers for PMXEVCNTR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 14:41 ` Christoffer Dall 2015-07-17 14:41 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 10/18] KVM: ARM64: Add reset and access handlers for PMCCNTR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 14:42 ` Christoffer Dall 2015-07-17 14:42 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 11/18] KVM: ARM64: Add reset and access handlers for PMCNTENSET_EL0 and PMCNTENCLR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 14:52 ` Christoffer Dall 2015-07-17 14:52 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 12/18] KVM: ARM64: Add reset and access handlers for PMINTENSET_EL1 and PMINTENCLR_EL1 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 14:56 ` Christoffer Dall 2015-07-17 14:56 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 13/18] KVM: ARM64: Add reset and access handlers for PMOVSSET_EL0 and PMOVSCLR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 14:59 ` Christoffer Dall 2015-07-17 14:59 ` Christoffer Dall 2015-07-17 15:02 ` Christoffer Dall 2015-07-17 15:02 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 14/18] KVM: ARM64: Add reset and access handlers for PMUSERENR_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 15:01 ` Christoffer Dall 2015-07-17 15:01 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 15/18] KVM: ARM64: Add reset and access handlers for PMSWINC_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 15:13 ` Christoffer Dall 2015-07-17 15:13 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 16/18] KVM: ARM64: Add access handlers for PMEVCNTRn_EL0 and PMEVTYPERn_EL0 register shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 15:19 ` Christoffer Dall 2015-07-17 15:19 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 17/18] KVM: ARM64: Add PMU overflow interrupt routing shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 15:28 ` Christoffer Dall 2015-07-17 15:28 ` Christoffer Dall 2015-07-06 2:17 ` [PATCH 18/18] KVM: ARM64: Add KVM_CAP_ARM_PMU and KVM_ARM_PMU_SET_IRQ shannon.zhao 2015-07-06 2:17 ` shannon.zhao at linaro.org 2015-07-17 15:32 ` Christoffer Dall 2015-07-17 15:32 ` Christoffer Dall
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