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From: Eddie Huang <eddie.huang@mediatek.com>
To: Wolfram Sang <wsa@the-dreams.de>
Cc: <srv_heupstream@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Liguo Zhang <liguo.zhang@mediatek.com>,
	Xudong Chen <xudong.chen@mediatek.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	<linux-i2c@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	Eddie Huang <eddie.huang@mediatek.com>
Subject: [PATCH 1/2] i2c: mediatek: Reset DMA engine in hardware init function
Date: Tue, 4 Aug 2015 19:44:52 +0800	[thread overview]
Message-ID: <1438688693-60275-2-git-send-email-eddie.huang@mediatek.com> (raw)
In-Reply-To: <1438688693-60275-1-git-send-email-eddie.huang@mediatek.com>

Reset DMA in hardware init function to avoid unknown hardware state
before do any I2C operation.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
---
 drivers/i2c/busses/i2c-mt65xx.c |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 9920eef..055159d 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2014 MediaTek Inc.
- * Author: Xudong Chen <xudong.chen@mediatek.com>
+ * Author:
+ *   Xudong Chen <xudong.chen@mediatek.com>
+ *   Liguo Zhang <liguo.zhang@mediatek.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -59,6 +61,7 @@
 #define I2C_DMA_START_EN		0x0001
 #define I2C_DMA_INT_FLAG_NONE		0x0000
 #define I2C_DMA_CLR_FLAG		0x0000
+#define I2C_DMA_HARD_RST		0x0002
 
 #define I2C_DEFAULT_SPEED		100000	/* hz */
 #define MAX_FS_MODE_SPEED		400000
@@ -81,6 +84,7 @@ enum DMA_REGS_OFFSET {
 	OFFSET_INT_FLAG = 0x0,
 	OFFSET_INT_EN = 0x04,
 	OFFSET_EN = 0x08,
+	OFFSET_RST = 0x0c,
 	OFFSET_CON = 0x18,
 	OFFSET_TX_MEM_ADDR = 0x1c,
 	OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +266,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 		      I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 	writew(control_reg, i2c->base + OFFSET_CONTROL);
 	writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+
+	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+	udelay(50);
+	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 }
 
 /*
-- 
1.7.9.5


WARNING: multiple messages have this Message-ID (diff)
From: Eddie Huang <eddie.huang@mediatek.com>
To: Wolfram Sang <wsa@the-dreams.de>
Cc: srv_heupstream@mediatek.com,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Liguo Zhang <liguo.zhang@mediatek.com>,
	Xudong Chen <xudong.chen@mediatek.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	Eddie Huang <eddie.huang@mediatek.com>
Subject: [PATCH 1/2] i2c: mediatek: Reset DMA engine in hardware init function
Date: Tue, 4 Aug 2015 19:44:52 +0800	[thread overview]
Message-ID: <1438688693-60275-2-git-send-email-eddie.huang@mediatek.com> (raw)
In-Reply-To: <1438688693-60275-1-git-send-email-eddie.huang@mediatek.com>

Reset DMA in hardware init function to avoid unknown hardware state
before do any I2C operation.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
---
 drivers/i2c/busses/i2c-mt65xx.c |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 9920eef..055159d 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2014 MediaTek Inc.
- * Author: Xudong Chen <xudong.chen@mediatek.com>
+ * Author:
+ *   Xudong Chen <xudong.chen@mediatek.com>
+ *   Liguo Zhang <liguo.zhang@mediatek.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -59,6 +61,7 @@
 #define I2C_DMA_START_EN		0x0001
 #define I2C_DMA_INT_FLAG_NONE		0x0000
 #define I2C_DMA_CLR_FLAG		0x0000
+#define I2C_DMA_HARD_RST		0x0002
 
 #define I2C_DEFAULT_SPEED		100000	/* hz */
 #define MAX_FS_MODE_SPEED		400000
@@ -81,6 +84,7 @@ enum DMA_REGS_OFFSET {
 	OFFSET_INT_FLAG = 0x0,
 	OFFSET_INT_EN = 0x04,
 	OFFSET_EN = 0x08,
+	OFFSET_RST = 0x0c,
 	OFFSET_CON = 0x18,
 	OFFSET_TX_MEM_ADDR = 0x1c,
 	OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +266,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 		      I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 	writew(control_reg, i2c->base + OFFSET_CONTROL);
 	writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+
+	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+	udelay(50);
+	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 }
 
 /*
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: eddie.huang@mediatek.com (Eddie Huang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] i2c: mediatek: Reset DMA engine in hardware init function
Date: Tue, 4 Aug 2015 19:44:52 +0800	[thread overview]
Message-ID: <1438688693-60275-2-git-send-email-eddie.huang@mediatek.com> (raw)
In-Reply-To: <1438688693-60275-1-git-send-email-eddie.huang@mediatek.com>

Reset DMA in hardware init function to avoid unknown hardware state
before do any I2C operation.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
---
 drivers/i2c/busses/i2c-mt65xx.c |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 9920eef..055159d 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2014 MediaTek Inc.
- * Author: Xudong Chen <xudong.chen@mediatek.com>
+ * Author:
+ *   Xudong Chen <xudong.chen@mediatek.com>
+ *   Liguo Zhang <liguo.zhang@mediatek.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -59,6 +61,7 @@
 #define I2C_DMA_START_EN		0x0001
 #define I2C_DMA_INT_FLAG_NONE		0x0000
 #define I2C_DMA_CLR_FLAG		0x0000
+#define I2C_DMA_HARD_RST		0x0002
 
 #define I2C_DEFAULT_SPEED		100000	/* hz */
 #define MAX_FS_MODE_SPEED		400000
@@ -81,6 +84,7 @@ enum DMA_REGS_OFFSET {
 	OFFSET_INT_FLAG = 0x0,
 	OFFSET_INT_EN = 0x04,
 	OFFSET_EN = 0x08,
+	OFFSET_RST = 0x0c,
 	OFFSET_CON = 0x18,
 	OFFSET_TX_MEM_ADDR = 0x1c,
 	OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +266,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 		      I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 	writew(control_reg, i2c->base + OFFSET_CONTROL);
 	writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+
+	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+	udelay(50);
+	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 }
 
 /*
-- 
1.7.9.5

  reply	other threads:[~2015-08-04 11:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-04 11:44 [PATCH 0/2] Mediatek I2C fixup Eddie Huang
2015-08-04 11:44 ` Eddie Huang
2015-08-04 11:44 ` Eddie Huang
2015-08-04 11:44 ` Eddie Huang [this message]
2015-08-04 11:44   ` [PATCH 1/2] i2c: mediatek: Reset DMA engine in hardware init function Eddie Huang
2015-08-04 11:44   ` Eddie Huang
2015-08-04 11:44 ` [PATCH 2/2] i2c: mediatek: Fixup i2c ack error interrupt handling Eddie Huang
2015-08-04 11:44   ` Eddie Huang
2015-08-04 11:44   ` Eddie Huang

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