[PATCH 2/4] drm/i915: Use complete virtual address range on 32-bit platforms

[Michel Thierry <michel.thierry@intel.com>]

With the offset length being taken care of in ("drm/i915/gtt: Allow >=
4GB offsets in X86_32"), the code should be finally safe in 32-bit
kernels.

This reverts commit 501fd70fcaebc911b6b96a7b331e6960e5af67e7
Author: Michel Thierry <michel.thierry@intel.com>
Date:   Fri May 29 14:15:05 2015 +0100

    drm/i915: limit PPGTT size to 2GB in 32-bit platforms

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dee3b39..451913a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1495,14 +1495,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 			goto free_scratch;
 
 		ppgtt->base.total = 1ULL << 32;
-		if (IS_ENABLED(CONFIG_X86_32))
-			/* While we have a proliferation of size_t variables
-			 * we cannot represent the full ppgtt size on 32bit,
-			 * so limit it to the same size as the GGTT (currently
-			 * 2GiB).
-			 */
-			ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
-
 		ppgtt->switch_mm = gen8_legacy_mm_switch;
 		trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
 							      0, 0,
-- 
2.5.0

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