[PATCH 7/6] drm/i915/skl: DDI-E and DDI-A shares 4 lanes.

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

DDI-A and DDI-E shares the 4 lanes. So when DDI-E is present
we need to configure lane count propperly for both.

This was based on Sonika's
[PATCH] drm/i915/skl: Select DDIA lane capability based upon vbt

Credits-to: Sonika Jindal <sonika.jindal@intel.com>
Cc: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 12 ++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  |  8 +++++---
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 110d546..557cecf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3178,7 +3178,15 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 	struct intel_digital_port *intel_dig_port;
 	struct intel_encoder *intel_encoder;
 	struct drm_encoder *encoder;
-	bool init_hdmi, init_dp;
+	bool init_hdmi, init_dp, ddi_e_present;
+
+	/*
+	 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
+	 */
+	ddie_present = IS_SKYLAKE(dev) &&
+		(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
+		 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
+		 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi);
 
 	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
 		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
@@ -3210,7 +3218,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 	intel_dig_port->port = port;
 	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
 					  (DDI_BUF_PORT_REVERSAL |
-					   DDI_A_4_LANES);
+					   ddi_e_present ? 0 : DDI_A_4_LANES);
 
 	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3ff2080..7ada79e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -159,9 +159,11 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 	u8 source_max, sink_max;
 
 	source_max = 4;
-	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
-	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
-		source_max = 2;
+	if (HAS_DDI(dev) && (intel_dig_port->port == PORT_E ||
+			     (intel_dig_port->port == PORT_A &&
+			      (intel_dig_port->saved_port_bits &
+			       DDI_A_4_LANES) == 0))
+	    source_max = 2;
 
 	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 
-- 
2.4.3

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