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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: access the PP_CONTROL reg only pre GEN5
Date: Thu,  3 Sep 2015 16:24:35 +0300	[thread overview]
Message-ID: <1441286676-26630-1-git-send-email-imre.deak@intel.com> (raw)

This register exists only pre GEN5, but atm we also access it on
VLV/BXT/CHV. Prevent accessing it on these latter platforms.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_lvds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 0794dc8..a16308a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -955,7 +955,7 @@ void intel_lvds_init(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev)) {
 		I915_WRITE(PCH_PP_CONTROL,
 			   I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
-	} else {
+	} else if (INTEL_INFO(dev_priv)->gen < 5) {
 		I915_WRITE(PP_CONTROL,
 			   I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
 	}
-- 
2.1.4

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             reply	other threads:[~2015-09-03 13:24 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-03 13:24 Imre Deak [this message]
2015-09-03 13:24 ` [PATCH v2 2/2] drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5 Imre Deak
2015-09-03 13:41   ` Ville Syrjälä
2015-09-04  8:19     ` Daniel Vetter
2015-09-04  8:57   ` Jani Nikula
2015-09-03 13:40 ` [PATCH 1/2] drm/i915: access the PP_CONTROL reg " Ville Syrjälä
2015-09-03 13:48   ` Ville Syrjälä

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