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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: "Chris Wilson" <chris@chris-wilson.co.uk>,
	"Michał Winiarski" <michal.winiarski@intel.com>,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	stable@vger.kernel.org
Subject: [PATCH v2] drm/i915: Limit the number of loops for reading a split 64bit register
Date: Tue,  8 Sep 2015 14:17:13 +0100	[thread overview]
Message-ID: <1441718233-29112-1-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <8737ypnl4f.fsf@intel.com>

In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
reads. Due to the nature of the registers we try to read in this manner,
they may increment between the two instruction (e.g. a timestamp
counter). To keep the result accurate, we repeat the read if we detect
an overflow (i.e. the upper value varies). However, some harware is just
plain flaky and may endless loop as the the upper 32bits are not stable.
Just give up after a couple of tries and report whatever we read last.

v2: Use the most recent values when erring out on an unstable register.

Reported-by: russianneuromancer@ya.ru
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12870073d58f..51a88e70a6f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 #define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
 
 #define I915_READ64_2x32(lower_reg, upper_reg) ({			\
-	u32 upper, lower, tmp;						\
-	tmp = I915_READ(upper_reg);					\
+	u32 upper, lower, old_upper, loop = 0;				\
+	upper = I915_READ(upper_reg);					\
 	do {								\
-		upper = tmp;						\
+		old_upper = upper;					\
 		lower = I915_READ(lower_reg);				\
-		tmp = I915_READ(upper_reg);				\
-	} while (upper != tmp);						\
+		upper = I915_READ(upper_reg);				\
+	} while (upper != old_upper && loop++ < 2);			\
 	(u64)upper << 32 | lower; })
 
 #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
-- 
2.5.1


  parent reply	other threads:[~2015-09-08 13:17 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-08  7:24 [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register Chris Wilson
2015-09-08  7:51 ` Chris Wilson
2015-09-08  9:29   ` Daniel Vetter
2015-09-08  9:29     ` Daniel Vetter
2015-09-08 12:36 ` [Intel-gfx] " Jani Nikula
2015-09-08 12:36   ` Jani Nikula
2015-09-08 13:10   ` [Intel-gfx] " Chris Wilson
2015-09-08 13:17   ` Chris Wilson [this message]
2015-09-08 19:00     ` [PATCH v2] " Daniel Vetter
2015-09-08 19:00       ` Daniel Vetter
2015-09-09  8:13       ` Jani Nikula
2015-09-09  8:13         ` Jani Nikula

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