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From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Akash Goel <akash.goel@intel.com>
Subject: [PATCH 1/3] drm/i915: WaRsUseTimeoutMode
Date: Fri, 11 Sep 2015 17:53:06 +0530	[thread overview]
Message-ID: <1441974188-1631-1-git-send-email-sagar.a.kamble@intel.com> (raw)

Enable TO mode for RC6 for SKL till D0 and BXT till A0.

Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c93d3a7..6e4818d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
 		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
 	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
 			"on" : "off");
-	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-				   GEN6_RC_CTL_EI_MODE(1) |
-				   rc6_mask);
+
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
+		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
+                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                                GEN7_RC_CTL_TO_MODE |
+                                rc6_mask);
+        else
+                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                                GEN6_RC_CTL_EI_MODE(1) |
+                                rc6_mask);
 
 	/*
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
-- 
1.9.1

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             reply	other threads:[~2015-09-11 12:21 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-11 12:23 Sagar Arun Kamble [this message]
2015-09-11 12:23 ` [PATCH 2/3] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating Sagar Arun Kamble
2015-09-11 12:23 ` [PATCH 3/3] drm/i915: Program GuC MAX IDLE Count Sagar Arun Kamble

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