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From: Zidan Wang <zidan.wang@freescale.com>
To: broonie@kernel.org
Cc: alsa-devel@alsa-project.org, timur@tabi.org,
	Zidan Wang <zidan.wang@freescale.com>,
	Xiubo.Lee@gmail.com, tiwai@suse.com, nicoleotsuka@gmail.com
Subject: [PATCH] ASoC: fsl_spdif: STL and STR registers are non volatile
Date: Mon, 26 Oct 2015 15:19:04 +0800	[thread overview]
Message-ID: <1445843945-13319-3-git-send-email-zidan.wang@freescale.com> (raw)
In-Reply-To: <1445843945-13319-1-git-send-email-zidan.wang@freescale.com>

STL and STR registers are writable and not readable. So they are non volatile.
Remove them from volatile list, and add default register value for them.

Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
---
 sound/soc/fsl/fsl_spdif.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 3d59bb6..28a8823 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -1006,12 +1006,14 @@ static const struct snd_soc_component_driver fsl_spdif_component = {
 
 /* FSL SPDIF REGMAP */
 static const struct reg_default fsl_spdif_reg_defaults[] = {
-	{0x0,  0x00000400},
-	{0x4,  0x00000000},
-	{0xc,  0x00000000},
-	{0x34, 0x00000000},
-	{0x38, 0x00000000},
-	{0x50, 0x00020f00},
+	{REG_SPDIF_SCR,    0x00000400},
+	{REG_SPDIF_SRCD,   0x00000000},
+	{REG_SPDIF_SIE,	   0x00000000},
+	{REG_SPDIF_STL,	   0x00000000},
+	{REG_SPDIF_STR,	   0x00000000},
+	{REG_SPDIF_STCSCH, 0x00000000},
+	{REG_SPDIF_STCSCL, 0x00000000},
+	{REG_SPDIF_STC,	   0x00020f00},
 };
 
 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
@@ -1049,8 +1051,6 @@ static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
 	case REG_SPDIF_SRCSL:
 	case REG_SPDIF_SRU:
 	case REG_SPDIF_SRQ:
-	case REG_SPDIF_STL:
-	case REG_SPDIF_STR:
 	case REG_SPDIF_SRFM:
 		return true;
 	default:
-- 
1.9.1

  parent reply	other threads:[~2015-10-26  7:17 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-26  7:19 [PATCH] ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile Zidan Wang
2015-10-26  7:19 ` [PATCH] ASoC: fsl-sai: add default register map for regmap cache Zidan Wang
2015-10-27 19:40   ` Nicolin Chen
2015-10-28  1:09   ` Applied "ASoC: fsl-sai: add default register map for regmap cache" to the asoc tree Mark Brown
2015-10-26  7:19 ` Zidan Wang [this message]
2015-10-28  1:09   ` Applied "ASoC: fsl_spdif: STL and STR registers are non volatile" " Mark Brown
2015-10-26  7:19 ` [PATCH] ASoC: fsl_ssi: using macro for default register map Zidan Wang
2015-10-28  1:09   ` Applied "ASoC: fsl_ssi: using macro for default register map" to the asoc tree Mark Brown
2015-10-28  1:09 ` Applied "ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile" " Mark Brown

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