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From: Alex Van Brunt <avanbrunt@nvidia.com>
To: linux-arm-kernel@lists.infradead.org,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	Will Deacon <will.deacon@arm.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>
Cc: Alex Van Brunt <avanbrunt@nvidia.com>, <stable@vger.kernel.org>
Subject: [PATCH v2 4/4] arm64: document the cache policy behavior
Date: Thu, 29 Oct 2015 16:20:42 -0700	[thread overview]
Message-ID: <1446160842-25787-4-git-send-email-avanbrunt@nvidia.com> (raw)
In-Reply-To: <1446160842-25787-1-git-send-email-avanbrunt@nvidia.com>

Add a comment that clairfies how the kernel should behave given the cache
policy reported by the CPU.

Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Cc: <stable@vger.kernel.org>
---
 arch/arm64/kernel/cpuinfo.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index ae04ac1..bf7e5e2 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -49,6 +49,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 	unsigned int cpu = smp_processor_id();
 	u32 l1ip = CTR_L1IP(info->reg_ctr);
 
+	/*
+	 * The ARM architecture defines PIPT, VIPT and AIVIVT in terms of the
+	 * the observable behavior not how the CPU implements the policy.
+	 * Specifically, the policies differentiate the correct way to
+	 * invalidate the cache. The definitions say that the only
+	 * architecturally guaranteed way to invalidate a VIPT or AIVIVT
+	 * instruction cache is to invalidate the entire instruction cache.
+	 */
 	if (l1ip != ICACHE_POLICY_PIPT)
 		set_bit(ICACHEF_ALIASING, &__icache_flags);
 	if (l1ip == ICACHE_POLICY_AIVIVT)
-- 
2.1.4


WARNING: multiple messages have this Message-ID (diff)
From: avanbrunt@nvidia.com (Alex Van Brunt)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 4/4] arm64: document the cache policy behavior
Date: Thu, 29 Oct 2015 16:20:42 -0700	[thread overview]
Message-ID: <1446160842-25787-4-git-send-email-avanbrunt@nvidia.com> (raw)
In-Reply-To: <1446160842-25787-1-git-send-email-avanbrunt@nvidia.com>

Add a comment that clairfies how the kernel should behave given the cache
policy reported by the CPU.

Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Cc: <stable@vger.kernel.org>
---
 arch/arm64/kernel/cpuinfo.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index ae04ac1..bf7e5e2 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -49,6 +49,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 	unsigned int cpu = smp_processor_id();
 	u32 l1ip = CTR_L1IP(info->reg_ctr);
 
+	/*
+	 * The ARM architecture defines PIPT, VIPT and AIVIVT in terms of the
+	 * the observable behavior not how the CPU implements the policy.
+	 * Specifically, the policies differentiate the correct way to
+	 * invalidate the cache. The definitions say that the only
+	 * architecturally guaranteed way to invalidate a VIPT or AIVIVT
+	 * instruction cache is to invalidate the entire instruction cache.
+	 */
 	if (l1ip != ICACHE_POLICY_PIPT)
 		set_bit(ICACHEF_ALIASING, &__icache_flags);
 	if (l1ip == ICACHE_POLICY_AIVIVT)
-- 
2.1.4

  parent reply	other threads:[~2015-10-29 23:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-29 23:20 [PATCH v2 1/4] Revert "arm64: kernel: add support for cpu cache information" Alex Van Brunt
2015-10-29 23:20 ` Alex Van Brunt
2015-10-29 23:20 ` [PATCH v2 2/4] Revert "arm64: don't flag non-aliasing VIPT I-caches as aliasing" Alex Van Brunt
2015-10-29 23:20   ` Alex Van Brunt
2015-10-29 23:20 ` [PATCH v2 3/4] Revert "arm64: add helper functions to read I-cache attributes" Alex Van Brunt
2015-10-29 23:20   ` Alex Van Brunt
2015-10-29 23:20 ` Alex Van Brunt [this message]
2015-10-29 23:20   ` [PATCH v2 4/4] arm64: document the cache policy behavior Alex Van Brunt
2015-10-30 12:08   ` Will Deacon
2015-10-30 12:08     ` Will Deacon

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