From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>
Cc: <linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
<marc.zyngier@arm.com>, <christoffer.dall@linaro.org>,
<will.deacon@arm.com>, <alex.bennee@linaro.org>, <wei@redhat.com>,
<cov@codeaurora.org>, <shannon.zhao@linaro.org>,
<peter.huangpeng@huawei.com>, <zhaoshenglong@huawei.com>
Subject: [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers
Date: Fri, 30 Oct 2015 14:21:45 +0800 [thread overview]
Message-ID: <1446186123-11548-4-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/include/asm/kvm_asm.h | 55 ++++++++++++++++++++++++++++++++++++----
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 5e37710..4f804c1 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -48,12 +48,34 @@
#define MDSCR_EL1 22 /* Monitor Debug System Control Register */
#define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */
+/* Performance Monitors Registers */
+#define PMCR_EL0 24 /* Control Register */
+#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */
+#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register */
+#define PMSELR_EL0 27 /* Event Counter Selection Register */
+#define PMCEID0_EL0 28 /* Common Event Identification Register 0 */
+#define PMCEID1_EL0 29 /* Common Event Identification Register 1 */
+#define PMEVCNTR0_EL0 30 /* Event Counter Register (0-30) */
+#define PMEVCNTR30_EL0 60
+#define PMCCNTR_EL0 61 /* Cycle Counter Register */
+#define PMEVTYPER0_EL0 62 /* Event Type Register (0-30) */
+#define PMEVTYPER30_EL0 92
+#define PMCCFILTR_EL0 93 /* Cycle Count Filter Register */
+#define PMXEVCNTR_EL0 94 /* Selected Event Count Register */
+#define PMXEVTYPER_EL0 95 /* Selected Event Type Register */
+#define PMCNTENSET_EL0 96 /* Count Enable Set Register */
+#define PMCNTENCLR_EL0 97 /* Count Enable Clear Register */
+#define PMINTENSET_EL1 98 /* Interrupt Enable Set Register */
+#define PMINTENCLR_EL1 99 /* Interrupt Enable Clear Register */
+#define PMUSERENR_EL0 100 /* User Enable Register */
+#define PMSWINC_EL0 101 /* Software Increment Register */
+
/* 32bit specific registers. Keep them at the end of the range */
-#define DACR32_EL2 24 /* Domain Access Control Register */
-#define IFSR32_EL2 25 /* Instruction Fault Status Register */
-#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
-#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
-#define NR_SYS_REGS 28
+#define DACR32_EL2 102 /* Domain Access Control Register */
+#define IFSR32_EL2 103 /* Instruction Fault Status Register */
+#define FPEXC32_EL2 104 /* Floating-Point Exception Control Register */
+#define DBGVCR32_EL2 105 /* Debug Vector Catch Register */
+#define NR_SYS_REGS 106
/* 32bit mapping */
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
@@ -75,6 +97,24 @@
#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
+
+/* Performance Monitors*/
+#define c9_PMCR (PMCR_EL0 * 2)
+#define c9_PMOVSSET (PMOVSSET_EL0 * 2)
+#define c9_PMOVSCLR (PMOVSCLR_EL0 * 2)
+#define c9_PMCCNTR (PMCCNTR_EL0 * 2)
+#define c9_PMSELR (PMSELR_EL0 * 2)
+#define c9_PMCEID0 (PMCEID0_EL0 * 2)
+#define c9_PMCEID1 (PMCEID1_EL0 * 2)
+#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2)
+#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2)
+#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2)
+#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2)
+#define c9_PMINTENSET (PMINTENSET_EL1 * 2)
+#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2)
+#define c9_PMUSERENR (PMUSERENR_EL0 * 2)
+#define c9_PMSWINC (PMSWINC_EL0 * 2)
+
#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
@@ -86,6 +126,11 @@
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+/* Performance Monitors*/
+#define c14_PMEVCNTR0 (PMEVCNTR0_EL0 * 2)
+#define c14_PMEVTYPER0 (PMEVTYPER0_EL0 * 2)
+#define c14_PMCCFILTR (PMCCFILTR_EL0 * 2)
+
#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
marc.zyngier@arm.com, christoffer.dall@linaro.org,
will.deacon@arm.com, alex.bennee@linaro.org, wei@redhat.com,
cov@codeaurora.org, shannon.zhao@linaro.org,
peter.huangpeng@huawei.com, zhaoshenglong@huawei.com
Subject: [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers
Date: Fri, 30 Oct 2015 14:21:45 +0800 [thread overview]
Message-ID: <1446186123-11548-4-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/include/asm/kvm_asm.h | 55 ++++++++++++++++++++++++++++++++++++----
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 5e37710..4f804c1 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -48,12 +48,34 @@
#define MDSCR_EL1 22 /* Monitor Debug System Control Register */
#define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */
+/* Performance Monitors Registers */
+#define PMCR_EL0 24 /* Control Register */
+#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */
+#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register */
+#define PMSELR_EL0 27 /* Event Counter Selection Register */
+#define PMCEID0_EL0 28 /* Common Event Identification Register 0 */
+#define PMCEID1_EL0 29 /* Common Event Identification Register 1 */
+#define PMEVCNTR0_EL0 30 /* Event Counter Register (0-30) */
+#define PMEVCNTR30_EL0 60
+#define PMCCNTR_EL0 61 /* Cycle Counter Register */
+#define PMEVTYPER0_EL0 62 /* Event Type Register (0-30) */
+#define PMEVTYPER30_EL0 92
+#define PMCCFILTR_EL0 93 /* Cycle Count Filter Register */
+#define PMXEVCNTR_EL0 94 /* Selected Event Count Register */
+#define PMXEVTYPER_EL0 95 /* Selected Event Type Register */
+#define PMCNTENSET_EL0 96 /* Count Enable Set Register */
+#define PMCNTENCLR_EL0 97 /* Count Enable Clear Register */
+#define PMINTENSET_EL1 98 /* Interrupt Enable Set Register */
+#define PMINTENCLR_EL1 99 /* Interrupt Enable Clear Register */
+#define PMUSERENR_EL0 100 /* User Enable Register */
+#define PMSWINC_EL0 101 /* Software Increment Register */
+
/* 32bit specific registers. Keep them at the end of the range */
-#define DACR32_EL2 24 /* Domain Access Control Register */
-#define IFSR32_EL2 25 /* Instruction Fault Status Register */
-#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
-#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
-#define NR_SYS_REGS 28
+#define DACR32_EL2 102 /* Domain Access Control Register */
+#define IFSR32_EL2 103 /* Instruction Fault Status Register */
+#define FPEXC32_EL2 104 /* Floating-Point Exception Control Register */
+#define DBGVCR32_EL2 105 /* Debug Vector Catch Register */
+#define NR_SYS_REGS 106
/* 32bit mapping */
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
@@ -75,6 +97,24 @@
#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
+
+/* Performance Monitors*/
+#define c9_PMCR (PMCR_EL0 * 2)
+#define c9_PMOVSSET (PMOVSSET_EL0 * 2)
+#define c9_PMOVSCLR (PMOVSCLR_EL0 * 2)
+#define c9_PMCCNTR (PMCCNTR_EL0 * 2)
+#define c9_PMSELR (PMSELR_EL0 * 2)
+#define c9_PMCEID0 (PMCEID0_EL0 * 2)
+#define c9_PMCEID1 (PMCEID1_EL0 * 2)
+#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2)
+#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2)
+#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2)
+#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2)
+#define c9_PMINTENSET (PMINTENSET_EL1 * 2)
+#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2)
+#define c9_PMUSERENR (PMUSERENR_EL0 * 2)
+#define c9_PMSWINC (PMSWINC_EL0 * 2)
+
#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
@@ -86,6 +126,11 @@
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+/* Performance Monitors*/
+#define c14_PMEVCNTR0 (PMEVCNTR0_EL0 * 2)
+#define c14_PMEVTYPER0 (PMEVTYPER0_EL0 * 2)
+#define c14_PMCCFILTR (PMCCFILTR_EL0 * 2)
+
#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers
Date: Fri, 30 Oct 2015 14:21:45 +0800 [thread overview]
Message-ID: <1446186123-11548-4-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/include/asm/kvm_asm.h | 55 ++++++++++++++++++++++++++++++++++++----
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 5e37710..4f804c1 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -48,12 +48,34 @@
#define MDSCR_EL1 22 /* Monitor Debug System Control Register */
#define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */
+/* Performance Monitors Registers */
+#define PMCR_EL0 24 /* Control Register */
+#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */
+#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register */
+#define PMSELR_EL0 27 /* Event Counter Selection Register */
+#define PMCEID0_EL0 28 /* Common Event Identification Register 0 */
+#define PMCEID1_EL0 29 /* Common Event Identification Register 1 */
+#define PMEVCNTR0_EL0 30 /* Event Counter Register (0-30) */
+#define PMEVCNTR30_EL0 60
+#define PMCCNTR_EL0 61 /* Cycle Counter Register */
+#define PMEVTYPER0_EL0 62 /* Event Type Register (0-30) */
+#define PMEVTYPER30_EL0 92
+#define PMCCFILTR_EL0 93 /* Cycle Count Filter Register */
+#define PMXEVCNTR_EL0 94 /* Selected Event Count Register */
+#define PMXEVTYPER_EL0 95 /* Selected Event Type Register */
+#define PMCNTENSET_EL0 96 /* Count Enable Set Register */
+#define PMCNTENCLR_EL0 97 /* Count Enable Clear Register */
+#define PMINTENSET_EL1 98 /* Interrupt Enable Set Register */
+#define PMINTENCLR_EL1 99 /* Interrupt Enable Clear Register */
+#define PMUSERENR_EL0 100 /* User Enable Register */
+#define PMSWINC_EL0 101 /* Software Increment Register */
+
/* 32bit specific registers. Keep them at the end of the range */
-#define DACR32_EL2 24 /* Domain Access Control Register */
-#define IFSR32_EL2 25 /* Instruction Fault Status Register */
-#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
-#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
-#define NR_SYS_REGS 28
+#define DACR32_EL2 102 /* Domain Access Control Register */
+#define IFSR32_EL2 103 /* Instruction Fault Status Register */
+#define FPEXC32_EL2 104 /* Floating-Point Exception Control Register */
+#define DBGVCR32_EL2 105 /* Debug Vector Catch Register */
+#define NR_SYS_REGS 106
/* 32bit mapping */
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
@@ -75,6 +97,24 @@
#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
+
+/* Performance Monitors*/
+#define c9_PMCR (PMCR_EL0 * 2)
+#define c9_PMOVSSET (PMOVSSET_EL0 * 2)
+#define c9_PMOVSCLR (PMOVSCLR_EL0 * 2)
+#define c9_PMCCNTR (PMCCNTR_EL0 * 2)
+#define c9_PMSELR (PMSELR_EL0 * 2)
+#define c9_PMCEID0 (PMCEID0_EL0 * 2)
+#define c9_PMCEID1 (PMCEID1_EL0 * 2)
+#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2)
+#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2)
+#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2)
+#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2)
+#define c9_PMINTENSET (PMINTENSET_EL1 * 2)
+#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2)
+#define c9_PMUSERENR (PMUSERENR_EL0 * 2)
+#define c9_PMSWINC (PMSWINC_EL0 * 2)
+
#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
@@ -86,6 +126,11 @@
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+/* Performance Monitors*/
+#define c14_PMEVCNTR0 (PMEVCNTR0_EL0 * 2)
+#define c14_PMEVTYPER0 (PMEVTYPER0_EL0 * 2)
+#define c14_PMCCFILTR (PMCCFILTR_EL0 * 2)
+
#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
--
2.0.4
next prev parent reply other threads:[~2015-10-30 6:23 UTC|newest]
Thread overview: 142+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-30 6:21 [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao [this message]
2015-10-30 6:21 ` [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-11-30 18:11 ` Marc Zyngier
2015-11-30 18:11 ` Marc Zyngier
2015-11-30 18:11 ` Marc Zyngier
2015-10-30 6:21 ` [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-11-02 20:06 ` Christopher Covington
2015-11-02 20:06 ` Christopher Covington
2015-11-30 17:56 ` Marc Zyngier
2015-11-30 17:56 ` Marc Zyngier
2015-12-01 1:51 ` Shannon Zhao
2015-12-01 1:51 ` Shannon Zhao
2015-12-01 8:49 ` Marc Zyngier
2015-12-01 8:49 ` Marc Zyngier
2015-12-01 12:46 ` Shannon Zhao
2015-12-01 12:46 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-11-30 11:42 ` Marc Zyngier
2015-11-30 11:42 ` Marc Zyngier
2015-11-30 11:59 ` Shannon Zhao
2015-11-30 11:59 ` Shannon Zhao
2015-11-30 13:19 ` Marc Zyngier
2015-11-30 13:19 ` Marc Zyngier
2015-11-30 13:19 ` Marc Zyngier
2015-10-30 6:21 ` [PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-11-02 20:13 ` Christopher Covington
2015-11-02 20:13 ` Christopher Covington
2015-11-03 2:33 ` Shannon Zhao
2015-11-03 2:33 ` Shannon Zhao
2015-11-03 2:33 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-11-02 20:54 ` Christopher Covington
2015-11-02 20:54 ` Christopher Covington
2015-11-03 2:41 ` Shannon Zhao
2015-11-03 2:41 ` Shannon Zhao
2015-11-03 2:41 ` Shannon Zhao
2015-11-30 18:12 ` Marc Zyngier
2015-11-30 18:12 ` Marc Zyngier
2015-11-30 18:12 ` Marc Zyngier
2015-12-01 2:42 ` Shannon Zhao
2015-12-01 2:42 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-10-30 6:21 ` Shannon Zhao
2015-11-02 21:20 ` Christopher Covington
2015-11-02 21:20 ` Christopher Covington
2015-10-30 6:22 ` [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 12:08 ` kbuild test robot
2015-10-30 12:08 ` kbuild test robot
2015-10-30 12:08 ` kbuild test robot
2015-10-31 2:06 ` Shannon Zhao
2015-10-31 2:06 ` Shannon Zhao
2015-11-30 18:22 ` Marc Zyngier
2015-11-30 18:22 ` Marc Zyngier
2015-11-30 18:22 ` Marc Zyngier
2015-12-01 14:35 ` Shannon Zhao
2015-12-01 14:35 ` Shannon Zhao
2015-12-01 14:50 ` Marc Zyngier
2015-12-01 14:50 ` Marc Zyngier
2015-12-01 15:13 ` Shannon Zhao
2015-12-01 15:13 ` Shannon Zhao
2015-12-01 15:41 ` Marc Zyngier
2015-12-01 15:41 ` Marc Zyngier
2015-12-01 16:26 ` Shannon Zhao
2015-12-01 16:26 ` Shannon Zhao
2015-12-01 16:57 ` Marc Zyngier
2015-12-01 16:57 ` Marc Zyngier
2015-12-02 2:40 ` Shannon Zhao
2015-12-02 2:40 ` Shannon Zhao
2015-12-02 8:45 ` Marc Zyngier
2015-12-02 8:45 ` Marc Zyngier
2015-12-02 9:49 ` Shannon Zhao
2015-12-02 9:49 ` Shannon Zhao
2015-12-02 10:22 ` Marc Zyngier
2015-12-02 10:22 ` Marc Zyngier
2015-12-02 16:27 ` Christoffer Dall
2015-12-02 16:27 ` Christoffer Dall
2015-10-30 6:22 ` [PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 6:22 ` [PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 6:22 ` [PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-10-30 6:22 ` Shannon Zhao
2015-11-30 18:31 ` Marc Zyngier
2015-11-30 18:31 ` Marc Zyngier
2015-11-30 18:31 ` Marc Zyngier
2015-11-30 18:34 ` [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-11-30 18:34 ` Marc Zyngier
2015-11-30 18:34 ` Marc Zyngier
2015-12-01 1:52 ` Shannon Zhao
2015-12-01 1:52 ` Shannon Zhao
2015-12-01 1:52 ` Shannon Zhao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1446186123-11548-4-git-send-email-zhaoshenglong@huawei.com \
--to=zhaoshenglong@huawei.com \
--cc=alex.bennee@linaro.org \
--cc=christoffer.dall@linaro.org \
--cc=cov@codeaurora.org \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=peter.huangpeng@huawei.com \
--cc=shannon.zhao@linaro.org \
--cc=wei@redhat.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.