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From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>
Cc: <linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<marc.zyngier@arm.com>, <christoffer.dall@linaro.org>,
	<will.deacon@arm.com>, <alex.bennee@linaro.org>, <wei@redhat.com>,
	<cov@codeaurora.org>, <shannon.zhao@linaro.org>,
	<peter.huangpeng@huawei.com>, <zhaoshenglong@huawei.com>
Subject: [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register
Date: Fri, 30 Oct 2015 14:21:47 +0800	[thread overview]
Message-ID: <1446186123-11548-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the acsessing action
specially, it uses default case to emulate writing and reading PMSELR
register.

Add a helper for CP15 registers reset to UNKNOWN.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 5 +++--
 arch/arm64/kvm/sys_regs.h | 8 ++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 5b591d6..35d232e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -707,7 +707,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMSELR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-	  trap_raz_wi },
+	  access_pmu_regs, reset_unknown, PMSELR_EL0 },
 	/* PMCEID0_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 	  trap_raz_wi },
@@ -998,7 +998,8 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
+	  reset_unknown_cp15, c9_PMSELR },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index eaa324e..8afeff7 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -110,6 +110,14 @@ static inline void reset_unknown(struct kvm_vcpu *vcpu,
 	vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
 }
 
+static inline void reset_unknown_cp15(struct kvm_vcpu *vcpu,
+				      const struct sys_reg_desc *r)
+{
+	BUG_ON(!r->reg);
+	BUG_ON(r->reg >= NR_COPRO_REGS);
+	vcpu_cp15(vcpu, r->reg) = 0xdecafbad;
+}
+
 static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
 	BUG_ON(!r->reg);
-- 
2.0.4



WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
	marc.zyngier@arm.com, christoffer.dall@linaro.org,
	will.deacon@arm.com, alex.bennee@linaro.org, wei@redhat.com,
	cov@codeaurora.org, shannon.zhao@linaro.org,
	peter.huangpeng@huawei.com, zhaoshenglong@huawei.com
Subject: [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register
Date: Fri, 30 Oct 2015 14:21:47 +0800	[thread overview]
Message-ID: <1446186123-11548-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the acsessing action
specially, it uses default case to emulate writing and reading PMSELR
register.

Add a helper for CP15 registers reset to UNKNOWN.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 5 +++--
 arch/arm64/kvm/sys_regs.h | 8 ++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 5b591d6..35d232e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -707,7 +707,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMSELR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-	  trap_raz_wi },
+	  access_pmu_regs, reset_unknown, PMSELR_EL0 },
 	/* PMCEID0_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 	  trap_raz_wi },
@@ -998,7 +998,8 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
+	  reset_unknown_cp15, c9_PMSELR },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index eaa324e..8afeff7 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -110,6 +110,14 @@ static inline void reset_unknown(struct kvm_vcpu *vcpu,
 	vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
 }
 
+static inline void reset_unknown_cp15(struct kvm_vcpu *vcpu,
+				      const struct sys_reg_desc *r)
+{
+	BUG_ON(!r->reg);
+	BUG_ON(r->reg >= NR_COPRO_REGS);
+	vcpu_cp15(vcpu, r->reg) = 0xdecafbad;
+}
+
 static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
 	BUG_ON(!r->reg);
-- 
2.0.4



WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register
Date: Fri, 30 Oct 2015 14:21:47 +0800	[thread overview]
Message-ID: <1446186123-11548-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the acsessing action
specially, it uses default case to emulate writing and reading PMSELR
register.

Add a helper for CP15 registers reset to UNKNOWN.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 5 +++--
 arch/arm64/kvm/sys_regs.h | 8 ++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 5b591d6..35d232e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -707,7 +707,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMSELR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-	  trap_raz_wi },
+	  access_pmu_regs, reset_unknown, PMSELR_EL0 },
 	/* PMCEID0_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 	  trap_raz_wi },
@@ -998,7 +998,8 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
+	  reset_unknown_cp15, c9_PMSELR },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index eaa324e..8afeff7 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -110,6 +110,14 @@ static inline void reset_unknown(struct kvm_vcpu *vcpu,
 	vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
 }
 
+static inline void reset_unknown_cp15(struct kvm_vcpu *vcpu,
+				      const struct sys_reg_desc *r)
+{
+	BUG_ON(!r->reg);
+	BUG_ON(r->reg >= NR_COPRO_REGS);
+	vcpu_cp15(vcpu, r->reg) = 0xdecafbad;
+}
+
 static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
 	BUG_ON(!r->reg);
-- 
2.0.4

  parent reply	other threads:[~2015-10-30  6:29 UTC|newest]

Thread overview: 142+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-30  6:21 [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-10-30  6:21 ` Shannon Zhao
2015-10-30  6:21 ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-11-30 18:11   ` Marc Zyngier
2015-11-30 18:11     ` Marc Zyngier
2015-11-30 18:11     ` Marc Zyngier
2015-10-30  6:21 ` Shannon Zhao [this message]
2015-10-30  6:21   ` [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-11-02 20:06   ` Christopher Covington
2015-11-02 20:06     ` Christopher Covington
2015-11-30 17:56   ` Marc Zyngier
2015-11-30 17:56     ` Marc Zyngier
2015-12-01  1:51     ` Shannon Zhao
2015-12-01  1:51       ` Shannon Zhao
2015-12-01  8:49       ` Marc Zyngier
2015-12-01  8:49         ` Marc Zyngier
2015-12-01 12:46         ` Shannon Zhao
2015-12-01 12:46           ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-11-30 11:42   ` Marc Zyngier
2015-11-30 11:42     ` Marc Zyngier
2015-11-30 11:59     ` Shannon Zhao
2015-11-30 11:59       ` Shannon Zhao
2015-11-30 13:19       ` Marc Zyngier
2015-11-30 13:19         ` Marc Zyngier
2015-11-30 13:19         ` Marc Zyngier
2015-10-30  6:21 ` [PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-11-02 20:13   ` Christopher Covington
2015-11-02 20:13     ` Christopher Covington
2015-11-03  2:33     ` Shannon Zhao
2015-11-03  2:33       ` Shannon Zhao
2015-11-03  2:33       ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-11-02 20:54   ` Christopher Covington
2015-11-02 20:54     ` Christopher Covington
2015-11-03  2:41     ` Shannon Zhao
2015-11-03  2:41       ` Shannon Zhao
2015-11-03  2:41       ` Shannon Zhao
2015-11-30 18:12   ` Marc Zyngier
2015-11-30 18:12     ` Marc Zyngier
2015-11-30 18:12     ` Marc Zyngier
2015-12-01  2:42     ` Shannon Zhao
2015-12-01  2:42       ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-10-30  6:21   ` Shannon Zhao
2015-11-02 21:20   ` Christopher Covington
2015-11-02 21:20     ` Christopher Covington
2015-10-30  6:22 ` [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30 12:08   ` kbuild test robot
2015-10-30 12:08     ` kbuild test robot
2015-10-30 12:08     ` kbuild test robot
2015-10-31  2:06     ` Shannon Zhao
2015-10-31  2:06       ` Shannon Zhao
2015-11-30 18:22   ` Marc Zyngier
2015-11-30 18:22     ` Marc Zyngier
2015-11-30 18:22     ` Marc Zyngier
2015-12-01 14:35     ` Shannon Zhao
2015-12-01 14:35       ` Shannon Zhao
2015-12-01 14:50       ` Marc Zyngier
2015-12-01 14:50         ` Marc Zyngier
2015-12-01 15:13         ` Shannon Zhao
2015-12-01 15:13           ` Shannon Zhao
2015-12-01 15:41           ` Marc Zyngier
2015-12-01 15:41             ` Marc Zyngier
2015-12-01 16:26             ` Shannon Zhao
2015-12-01 16:26               ` Shannon Zhao
2015-12-01 16:57               ` Marc Zyngier
2015-12-01 16:57                 ` Marc Zyngier
2015-12-02  2:40                 ` Shannon Zhao
2015-12-02  2:40                   ` Shannon Zhao
2015-12-02  8:45                   ` Marc Zyngier
2015-12-02  8:45                     ` Marc Zyngier
2015-12-02  9:49                     ` Shannon Zhao
2015-12-02  9:49                       ` Shannon Zhao
2015-12-02 10:22                       ` Marc Zyngier
2015-12-02 10:22                         ` Marc Zyngier
2015-12-02 16:27                         ` Christoffer Dall
2015-12-02 16:27                           ` Christoffer Dall
2015-10-30  6:22 ` [PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30  6:22 ` [PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30  6:22 ` [PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-10-30  6:22   ` Shannon Zhao
2015-11-30 18:31   ` Marc Zyngier
2015-11-30 18:31     ` Marc Zyngier
2015-11-30 18:31     ` Marc Zyngier
2015-11-30 18:34 ` [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-11-30 18:34   ` Marc Zyngier
2015-11-30 18:34   ` Marc Zyngier
2015-12-01  1:52   ` Shannon Zhao
2015-12-01  1:52     ` Shannon Zhao
2015-12-01  1:52     ` Shannon Zhao

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