From: Chris Zhong <zyw@rock-chips.com> To: heiko@sntech.de, linux-rockchip@lists.infradead.org, mark.yao@rock-chips.com, treding@nvidia.com, emil.l.velikov@gmail.com Cc: airlied@linux.ie, ajaykumar.rs@samsung.com, rmk+kernel@arm.linux.org.uk, dri-devel@lists.freedesktop.org, Liu Ying <Ying.liu@freescale.com>, Liu Ying <Ying.Liu@freescale.com>, Chris Zhong <zyw@rock-chips.com>, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Date: Fri, 20 Nov 2015 16:15:31 +0800 [thread overview] Message-ID: <1448007339-10966-6-git-send-email-zyw@rock-chips.com> (raw) In-Reply-To: <1448007339-10966-1-git-send-email-zyw@rock-chips.com> From: Liu Ying <Ying.liu@freescale.com> This patch adds device tree bindings for Synopsys DesignWare MIPI DSI host controller DRM bridge driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- Changes in v4: remove gpr property from example, since it is noused now. add the description about ports Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge Changes in v2: None .../bindings/display/bridge/dw_mipi_dsi.txt | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt new file mode 100644 index 0000000..8572ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt @@ -0,0 +1,80 @@ +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +The controller is a digital core that implements all protocol functions +defined in the MIPI DSI specification, providing an interface between +the system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells: Should be <1>. + - #size-cells: Should be <0>. + - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi" + for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. A common compatible string + "snps,dw-mipi-dsi" should be appended for all SoCs. + - reg: Represent the physical address range of the controller. + - interrupts: Represent the controller's interrupt to the CPU(s). + - clocks, clock-names: Phandles to the controller's pll reference + clock(ref), configuration clock(cfg) and APB clock(pclk), as + described in [1]. + - port@[X]: SoC specific port nodes with endpoint definitions as defined + in Documentation/devicetree/bindings/media/video-interfaces.txt, + please refer to the SoC specific binding document: + * Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi-rockchip.txt + + +For more required properties, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +Required sub-nodes: + - A node to represent a DSI peripheral as described in [2]. + +For more required sub-nodes, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + +example: + gpr: iomuxc-gpr@020e0000 { + /* ... */ + }; + + mipi_dsi: mipi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "cfg", "pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + + panel { + compatible = "truly,tft480800-16-e-dsi"; + reg = <0>; + /* ... */ + }; + }; -- 2.6.3
WARNING: multiple messages have this Message-ID (diff)
From: Chris Zhong <zyw@rock-chips.com> To: heiko@sntech.de, linux-rockchip@lists.infradead.org, mark.yao@rock-chips.com, treding@nvidia.com, emil.l.velikov@gmail.com Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, Pawel Moll <pawel.moll@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>, Chris Zhong <zyw@rock-chips.com>, rmk+kernel@arm.linux.org.uk, ajaykumar.rs@samsung.com Subject: [PATCH v4 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Date: Fri, 20 Nov 2015 16:15:31 +0800 [thread overview] Message-ID: <1448007339-10966-6-git-send-email-zyw@rock-chips.com> (raw) In-Reply-To: <1448007339-10966-1-git-send-email-zyw@rock-chips.com> From: Liu Ying <Ying.liu@freescale.com> This patch adds device tree bindings for Synopsys DesignWare MIPI DSI host controller DRM bridge driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- Changes in v4: remove gpr property from example, since it is noused now. add the description about ports Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge Changes in v2: None .../bindings/display/bridge/dw_mipi_dsi.txt | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt new file mode 100644 index 0000000..8572ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt @@ -0,0 +1,80 @@ +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +The controller is a digital core that implements all protocol functions +defined in the MIPI DSI specification, providing an interface between +the system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells: Should be <1>. + - #size-cells: Should be <0>. + - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi" + for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. A common compatible string + "snps,dw-mipi-dsi" should be appended for all SoCs. + - reg: Represent the physical address range of the controller. + - interrupts: Represent the controller's interrupt to the CPU(s). + - clocks, clock-names: Phandles to the controller's pll reference + clock(ref), configuration clock(cfg) and APB clock(pclk), as + described in [1]. + - port@[X]: SoC specific port nodes with endpoint definitions as defined + in Documentation/devicetree/bindings/media/video-interfaces.txt, + please refer to the SoC specific binding document: + * Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi-rockchip.txt + + +For more required properties, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +Required sub-nodes: + - A node to represent a DSI peripheral as described in [2]. + +For more required sub-nodes, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + +example: + gpr: iomuxc-gpr@020e0000 { + /* ... */ + }; + + mipi_dsi: mipi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "cfg", "pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + + panel { + compatible = "truly,tft480800-16-e-dsi"; + reg = <0>; + /* ... */ + }; + }; -- 2.6.3 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2015-11-20 8:16 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-11-20 8:15 [PATCH v4 0/13] Add mipi dsi support for rk3288 Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` [PATCH v4 01/13] clk: rockchip: add id for mipidsi sclk on rk3288 Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-23 17:29 ` Heiko Stübner 2015-11-23 17:29 ` Heiko Stübner 2015-11-20 8:15 ` [PATCH v4 02/13] clk: rockchip: add mipidsi clocks " Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` [PATCH v4 03/13] drm/rockchip: return a true clock rate to adjusted_mode Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:57 ` Mark yao 2015-11-20 8:57 ` Mark yao 2015-11-20 8:57 ` Mark yao 2015-11-20 8:15 ` [PATCH v4 04/13] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong [this message] 2015-11-20 8:15 ` [PATCH v4 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Chris Zhong 2015-11-20 14:32 ` Rob Herring 2015-11-20 14:32 ` Rob Herring 2015-11-20 8:15 ` [PATCH v4 06/13] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 16:07 ` Thierry Reding 2015-11-20 16:07 ` Thierry Reding 2015-11-26 7:03 ` Chris Zhong 2015-11-26 7:03 ` Chris Zhong 2015-11-26 8:04 ` Thierry Reding 2015-11-26 8:04 ` Thierry Reding 2015-11-26 10:05 ` Chris Zhong 2015-11-26 10:05 ` Chris Zhong 2015-11-20 8:15 ` [PATCH v4 07/13] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` [PATCH v4 08/13] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` [PATCH v4 09/13] ARM: dts: rockchip: add rk3288 mipi_dsi nodes Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` [PATCH v4 10/13] of: add vendor prefix for boe Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-23 8:08 ` Thierry Reding 2015-11-23 8:08 ` Thierry Reding 2015-11-20 8:15 ` [PATCH v4 11/13] drm/panel: simple: Add support for BOE TV080WUM-NL0 Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-23 8:09 ` Thierry Reding 2015-11-23 8:09 ` Thierry Reding 2015-11-20 8:15 ` [PATCH v4 12/13] drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding Chris Zhong 2015-11-20 8:15 ` [PATCH v4 12/13] drm/panel: simple: Add boe, tv080wum-nl0 " Chris Zhong 2015-11-23 8:10 ` [PATCH v4 12/13] drm/panel: simple: Add boe,tv080wum-nl0 " Thierry Reding 2015-11-23 8:10 ` Thierry Reding 2015-11-20 8:15 ` [PATCH v4 13/13] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Chris Zhong 2015-11-20 8:15 ` Chris Zhong 2015-11-20 8:15 ` Chris Zhong
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