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From: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
To: Caleb Crome <caleb@crome.org>,
	Roberto Fichera <kernel@tekno-soft.it>,
	Markus Pargmann <mpa@pengutronix.de>,
	Fabio Estevam <fabio.estevam@freescale.com>,
	"shawn.guo@linaro.org" <shawn.guo@linaro.org>,
	alsa-devel@alsa-project.org, broonie@kernel.org,
	lgirdwood@gmail.com
Cc: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
Subject: [PATCH v2 2/6] ASoC: fsl_ssi: The IPG/5 limitation concerns the bitclk, not the sysclk.
Date: Thu, 26 Nov 2015 16:05:37 +0100	[thread overview]
Message-ID: <1448550341-11765-3-git-send-email-arnaud.mouiche@invoxia.com> (raw)
In-Reply-To: <1448550341-11765-1-git-send-email-arnaud.mouiche@invoxia.com>

im6sl reference manual 47.7.4:
"
Bit clock - Used to serially clock the data bits in and out of the SSI port.
This clock is either generated internally (from SSI's sys clock) or taken
from external clock source (through the Tx/Rx clock ports).
[...]
Care should be taken to ensure that the bit clock frequency (either
internally generated by dividing the SSI's sys clock or sourced from
external device through Tx/Rx clock ports) is never greater than 1/5
of the ipg_clk (from CCM) frequency.
"

Since, in master mode, the sysclk is a multiple of bitclk, we can
easily reach a high sysclk value, whereas keeping a reasonable bitclk.

ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1)
    yet ipg_clk/5 = 66Mhz/5 = 13.2

Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
---
 sound/soc/fsl/fsl_ssi.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 4e5d7db..b34c09f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -595,6 +595,15 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 	if (IS_ERR(ssi_private->baudclk))
 		return -EINVAL;
 
+	/*
+	 * Hardware limitation: The bclk rate must be
+	 * never greater than 1/5 IPG clock rate
+	 */
+	if (freq * 5 > clk_get_rate(ssi_private->clk)) {
+		dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
+		return -EINVAL;
+	}
+
 	baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
 
 	/* It should be already enough to divide clock by setting pm alone */
@@ -611,13 +620,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 		else
 			clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
 
-		/*
-		 * Hardware limitation: The bclk rate must be
-		 * never greater than 1/5 IPG clock rate
-		 */
-		if (clkrate * 5 > clk_get_rate(ssi_private->clk))
-			continue;
-
 		clkrate /= factor;
 		afreq = clkrate / (i + 1);
 
-- 
1.9.1

  parent reply	other threads:[~2015-11-26 15:06 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-26 15:05 [PATCH v2 0/6] ASoC: fsl_ssi: Fixing various channel slips and bad samples insertions Arnaud Mouiche
2015-11-26 15:05 ` [PATCH v2 1/6] ASoC: fsl_ssi: Real hardware channels max number is 32 Arnaud Mouiche
2015-12-07 12:44   ` Fabio Estevam
2016-05-13 12:26   ` Applied "ASoC: fsl_ssi: Real hardware channels max number is 32" to the asoc tree Mark Brown
2015-11-26 15:05 ` Arnaud Mouiche [this message]
2015-11-26 15:05 ` [PATCH v2 3/6] ASoC: fsl_ssi: Save a dev reference for dev_err() purpose Arnaud Mouiche
2015-11-26 15:05 ` [PATCH v2 4/6] ASoC: fsl_ssi: Fix samples being dropped as Playback startup Arnaud Mouiche
2015-11-26 15:05 ` [PATCH v2 5/6] ASoC: fsl_ssi: Fix channel slipping in Playback at startup Arnaud Mouiche
2016-05-13 12:25   ` Applied "ASoC: fsl_ssi: Fix channel slipping in Playback at startup" to the asoc tree Mark Brown
2015-11-26 15:05 ` [PATCH v2 6/6] ASoC: fsl_ssi: Fix channel slipping on capture (or playback) restart in full duplex Arnaud Mouiche
2015-12-07 12:41 ` [PATCH v2 0/6] ASoC: fsl_ssi: Fixing various channel slips and bad samples insertions arnaud.mouiche
2015-12-07 16:46   ` Caleb Crome

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