From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> To: Thomas Abraham <thomas.ab@samsung.com>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Mike Turquette <mturquette@baylibre.com>, Kukjin Kim <kgene.kim@samsung.com>, Kukjin Kim <kgene@kernel.org>, Viresh Kumar <viresh.kumar@linaro.org>, Krzysztof Kozlowski <k.kozlowski@samsung.com>, Ben Gamari <ben@smart-cactus.org> Cc: Tomasz Figa <tomasz.figa@gmail.com>, Lukasz Majewski <l.majewski@samsung.com>, Heiko Stuebner <heiko@sntech.de>, Chanwoo Choi <cw00.choi@samsung.com>, Kevin Hilman <khilman@linaro.org>, Javier Martinez Canillas <javier@osg.samsung.com>, Tobias Jakobi <tjakobi@math.uni-bielefeld.de>, Anand Moon <linux.amoon@gmail.com>, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH v5 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data Date: Thu, 10 Dec 2015 17:58:47 +0100 [thread overview] Message-ID: <1449766729-435-6-git-send-email-b.zolnierkie@samsung.com> (raw) In-Reply-To: <1449766729-435-1-git-send-email-b.zolnierkie@samsung.com> Fix cpu clock configuration data for Exynos5422/5800 SoCs (they use higher PCLK_DBG divider values than Exynos5420 and support additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@baylibre.com> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 2a92546..837329d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { { 0 }, }; +static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { + { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 0 }, +}; + #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ { 1300000, E5420_KFC_DIV(3, 5, 2), }, { 1200000, E5420_KFC_DIV(3, 5, 2), }, { 1100000, E5420_KFC_DIV(3, 5, 2), }, @@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", - mout_cpu_p[0], mout_cpu_p[1], 0x200, - exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + if (soc == EXYNOS5420) { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + } else { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); + } exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", mout_kfc_p[0], mout_kfc_p[1], 0x28200, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: b.zolnierkie@samsung.com (Bartlomiej Zolnierkiewicz) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data Date: Thu, 10 Dec 2015 17:58:47 +0100 [thread overview] Message-ID: <1449766729-435-6-git-send-email-b.zolnierkie@samsung.com> (raw) In-Reply-To: <1449766729-435-1-git-send-email-b.zolnierkie@samsung.com> Fix cpu clock configuration data for Exynos5422/5800 SoCs (they use higher PCLK_DBG divider values than Exynos5420 and support additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@baylibre.com> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 2a92546..837329d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { { 0 }, }; +static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { + { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 0 }, +}; + #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ { 1300000, E5420_KFC_DIV(3, 5, 2), }, { 1200000, E5420_KFC_DIV(3, 5, 2), }, { 1100000, E5420_KFC_DIV(3, 5, 2), }, @@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", - mout_cpu_p[0], mout_cpu_p[1], 0x200, - exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + if (soc == EXYNOS5420) { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + } else { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); + } exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", mout_kfc_p[0], mout_kfc_p[1], 0x28200, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); -- 1.9.1
next prev parent reply other threads:[~2015-12-10 17:00 UTC|newest] Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-12-10 16:58 [PATCH v5 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` [PATCH v5 1/7] ARM: dts: Exynos542x/5800: add cluster regulator supply properties Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-11 1:16 ` Krzysztof Kozlowski 2015-12-11 1:16 ` Krzysztof Kozlowski 2015-12-10 16:58 ` [PATCH v5 2/7] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` [PATCH v5 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-11 1:17 ` Krzysztof Kozlowski 2015-12-11 1:17 ` Krzysztof Kozlowski 2015-12-11 3:16 ` Viresh Kumar 2015-12-11 3:16 ` Viresh Kumar 2015-12-11 3:25 ` Javier Martinez Canillas 2015-12-11 3:25 ` Javier Martinez Canillas 2015-12-11 3:32 ` Viresh Kumar 2015-12-11 3:32 ` Viresh Kumar 2015-12-11 4:00 ` Krzysztof Kozlowski 2015-12-11 4:00 ` Krzysztof Kozlowski 2015-12-11 4:13 ` Viresh Kumar 2015-12-11 4:13 ` Viresh Kumar 2015-12-11 4:18 ` Krzysztof Kozlowski 2015-12-11 4:18 ` Krzysztof Kozlowski 2015-12-11 4:38 ` Viresh Kumar 2015-12-11 4:38 ` Viresh Kumar 2015-12-11 4:53 ` Krzysztof Kozlowski 2015-12-11 4:53 ` Krzysztof Kozlowski 2015-12-11 4:53 ` Javier Martinez Canillas 2015-12-11 4:53 ` Javier Martinez Canillas 2015-12-11 5:28 ` Krzysztof Kozlowski 2015-12-11 5:28 ` Krzysztof Kozlowski 2015-12-11 5:41 ` Viresh Kumar 2015-12-11 5:41 ` Viresh Kumar 2015-12-11 4:39 ` Viresh Kumar 2015-12-11 4:39 ` Viresh Kumar 2015-12-10 16:58 ` [PATCH v5 4/7] ARM: Exynos: use generic cpufreq driver for Exynos5420 Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-11 1:18 ` Krzysztof Kozlowski 2015-12-11 1:18 ` Krzysztof Kozlowski 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz [this message] 2015-12-10 16:58 ` [PATCH v5 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` [PATCH v5 6/7] ARM: dts: Exynos5800: fix CPU OPP Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-11 1:27 ` Krzysztof Kozlowski 2015-12-11 1:27 ` Krzysztof Kozlowski 2015-12-10 16:58 ` [PATCH v5 7/7] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800 Bartlomiej Zolnierkiewicz 2015-12-10 16:58 ` Bartlomiej Zolnierkiewicz 2015-12-11 1:27 ` Krzysztof Kozlowski 2015-12-11 1:27 ` Krzysztof Kozlowski 2015-12-11 1:34 ` [PATCH v5 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms Krzysztof Kozlowski 2015-12-11 1:34 ` Krzysztof Kozlowski
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