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From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>, <marc.zyngier@arm.com>,
	<christoffer.dall@linaro.org>
Cc: kvm@vger.kernel.org, will.deacon@arm.com,
	linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org
Subject: [PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register
Date: Tue, 15 Dec 2015 16:49:25 +0800	[thread overview]
Message-ID: <1450169379-12336-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1450169379-12336-1-git-send-email-zhaoshenglong@huawei.com>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9a06116..c21f91b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -473,6 +473,19 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 	return true;
 }
 
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+			  const struct sys_reg_desc *r)
+{
+	if (p->is_write) {
+		vcpu_sys_reg(vcpu, r->reg) = p->regval;
+	} else {
+		/* return PMSELR.SEL field */
+		p->regval = vcpu_sys_reg(vcpu, r->reg) & ARMV8_COUNTER_MASK;
+	}
+
+	return true;
+}
+
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
 	/* DBGBVRn_EL1 */						\
@@ -672,7 +685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMSELR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-	  trap_raz_wi },
+	  access_pmselr, reset_unknown, PMSELR_EL0 },
 	/* PMCEID0_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 	  trap_raz_wi },
@@ -923,7 +936,7 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
-- 
2.0.4

WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com,
	christoffer.dall@linaro.org
Cc: kvm@vger.kernel.org, will.deacon@arm.com,
	linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org
Subject: [PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register
Date: Tue, 15 Dec 2015 16:49:25 +0800	[thread overview]
Message-ID: <1450169379-12336-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1450169379-12336-1-git-send-email-zhaoshenglong@huawei.com>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9a06116..c21f91b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -473,6 +473,19 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 	return true;
 }
 
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+			  const struct sys_reg_desc *r)
+{
+	if (p->is_write) {
+		vcpu_sys_reg(vcpu, r->reg) = p->regval;
+	} else {
+		/* return PMSELR.SEL field */
+		p->regval = vcpu_sys_reg(vcpu, r->reg) & ARMV8_COUNTER_MASK;
+	}
+
+	return true;
+}
+
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
 	/* DBGBVRn_EL1 */						\
@@ -672,7 +685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMSELR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-	  trap_raz_wi },
+	  access_pmselr, reset_unknown, PMSELR_EL0 },
 	/* PMCEID0_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 	  trap_raz_wi },
@@ -923,7 +936,7 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
-- 
2.0.4

WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register
Date: Tue, 15 Dec 2015 16:49:25 +0800	[thread overview]
Message-ID: <1450169379-12336-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1450169379-12336-1-git-send-email-zhaoshenglong@huawei.com>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9a06116..c21f91b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -473,6 +473,19 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 	return true;
 }
 
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+			  const struct sys_reg_desc *r)
+{
+	if (p->is_write) {
+		vcpu_sys_reg(vcpu, r->reg) = p->regval;
+	} else {
+		/* return PMSELR.SEL field */
+		p->regval = vcpu_sys_reg(vcpu, r->reg) & ARMV8_COUNTER_MASK;
+	}
+
+	return true;
+}
+
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
 	/* DBGBVRn_EL1 */						\
@@ -672,7 +685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMSELR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-	  trap_raz_wi },
+	  access_pmselr, reset_unknown, PMSELR_EL0 },
 	/* PMCEID0_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 	  trap_raz_wi },
@@ -923,7 +936,7 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
-- 
2.0.4

  parent reply	other threads:[~2015-12-15  8:49 UTC|newest]

Thread overview: 135+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-15  8:49 [PATCH v7 00/19] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-12-15  8:49 ` Shannon Zhao
2015-12-15  8:49 ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 11:34   ` Marc Zyngier
2015-12-15 11:34     ` Marc Zyngier
2015-12-15 11:44     ` Shannon Zhao
2015-12-15 11:44       ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 02/19] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 03/19] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 04/19] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` Shannon Zhao [this message]
2015-12-15  8:49   ` [PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 06/19] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 14:20   ` Marc Zyngier
2015-12-15 14:20     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-17 15:22   ` Mark Rutland
2015-12-17 15:22     ` Mark Rutland
2015-12-17 15:30     ` Marc Zyngier
2015-12-17 15:30       ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 13:43   ` Marc Zyngier
2015-12-15 13:43     ` Marc Zyngier
2015-12-15 14:26   ` Marc Zyngier
2015-12-15 14:26     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 13:44   ` Marc Zyngier
2015-12-15 13:44     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 13:56   ` Marc Zyngier
2015-12-15 13:56     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 14:02   ` Marc Zyngier
2015-12-15 14:02     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 14:06   ` Marc Zyngier
2015-12-15 14:06     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 14:36   ` Marc Zyngier
2015-12-15 14:36     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 14/19] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 14:58   ` Marc Zyngier
2015-12-15 14:58     ` Marc Zyngier
2015-12-15 15:59     ` Shannon Zhao
2015-12-15 15:59       ` Shannon Zhao
2015-12-15 16:02       ` Marc Zyngier
2015-12-15 16:02         ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 16/19] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 15:19   ` Marc Zyngier
2015-12-15 15:19     ` Marc Zyngier
2015-12-15  8:49 ` [PATCH v7 17/19] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 18/19] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49 ` [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15  8:49   ` Shannon Zhao
2015-12-15 15:33   ` Marc Zyngier
2015-12-15 15:33     ` Marc Zyngier
2015-12-15 15:50     ` Shannon Zhao
2015-12-15 15:50       ` Shannon Zhao
2015-12-15 15:59       ` Marc Zyngier
2015-12-15 15:59         ` Marc Zyngier
2015-12-15 17:50         ` Andrew Jones
2015-12-15 17:50           ` Andrew Jones
2015-12-15 17:50           ` [Qemu-devel] " Andrew Jones
2015-12-15 20:47         ` Christoffer Dall
2015-12-15 20:47           ` Christoffer Dall
2015-12-16  7:31           ` Shannon Zhao
2015-12-16  7:31             ` Shannon Zhao
2015-12-16  7:31             ` Shannon Zhao
2015-12-16  8:06             ` Shannon Zhao
2015-12-16  8:06               ` Shannon Zhao
2015-12-16  9:04               ` Marc Zyngier
2015-12-16  9:04                 ` Marc Zyngier
2015-12-16  9:29                 ` Shannon Zhao
2015-12-16  9:29                   ` Shannon Zhao
2015-12-16  9:29                   ` Shannon Zhao
2015-12-16 20:33               ` Christoffer Dall
2015-12-16 20:33                 ` Christoffer Dall
2015-12-17  7:22                 ` Shannon Zhao
2015-12-17  7:22                   ` Shannon Zhao
2015-12-17  7:22                   ` Shannon Zhao
2015-12-17  8:33                   ` Marc Zyngier
2015-12-17  8:33                     ` Marc Zyngier
2015-12-17  8:33                     ` Marc Zyngier
2015-12-17  8:41                     ` Shannon Zhao
2015-12-17  8:41                       ` Shannon Zhao
2015-12-17  8:41                       ` Shannon Zhao
2015-12-17  9:38                       ` Marc Zyngier
2015-12-17  9:38                         ` Marc Zyngier
2015-12-17 10:10                         ` Shannon Zhao
2015-12-17 10:10                           ` Shannon Zhao
2015-12-17 10:10                           ` Shannon Zhao
2015-12-17 10:38                           ` Marc Zyngier
2015-12-17 10:38                             ` Marc Zyngier
2015-12-18 10:00                   ` Christoffer Dall
2015-12-18 10:00                     ` Christoffer Dall
2015-12-15 15:41 ` [PATCH v7 00/19] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-12-15 15:41   ` Marc Zyngier

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