From: Gerd Hoffmann <kraxel@redhat.com> To: qemu-devel@nongnu.org Cc: igvt-g@ml01.01.org, xen-devel@lists.xensource.com, Eduardo Habkost <ehabkost@redhat.com>, Stefano Stabellini <stefano.stabellini@eu.citrix.com>, "Michael S. Tsirkin" <mst@redhat.com>, Cao jin <caoj.fnst@cn.fujitsu.com>, vfio-users@redhat.com, Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <rth@twiddle.net>, Gerd Hoffmann <kraxel@redhat.com> Subject: [Qemu-devel] [PATCH v3 09/11] igd: move igd-passthrough-isa-bridge to igd.c too Date: Tue, 5 Jan 2016 12:41:36 +0100 [thread overview] Message-ID: <1451994098-6972-10-git-send-email-kraxel@redhat.com> (raw) In-Reply-To: <1451994098-6972-1-git-send-email-kraxel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> --- hw/i386/pc_piix.c | 113 ------------------------------------------------------ hw/pci-host/igd.c | 108 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+), 113 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6532e32..f36222e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -914,119 +914,6 @@ static void pc_i440fx_0_10_machine_options(MachineClass *m) DEFINE_I440FX_MACHINE(v0_10, "pc-0.10", pc_compat_0_13, pc_i440fx_0_10_machine_options); -typedef struct { - uint16_t gpu_device_id; - uint16_t pch_device_id; - uint8_t pch_revision_id; -} IGDDeviceIDInfo; - -/* In real world different GPU should have different PCH. But actually - * the different PCH DIDs likely map to different PCH SKUs. We do the - * same thing for the GPU. For PCH, the different SKUs are going to be - * all the same silicon design and implementation, just different - * features turn on and off with fuses. The SW interfaces should be - * consistent across all SKUs in a given family (eg LPT). But just same - * features may not be supported. - * - * Most of these different PCH features probably don't matter to the - * Gfx driver, but obviously any difference in display port connections - * will so it should be fine with any PCH in case of passthrough. - * - * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell) - * scenarios, 0x9cc3 for BDW(Broadwell). - */ -static const IGDDeviceIDInfo igd_combo_id_infos[] = { - /* HSW Classic */ - {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */ - {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */ - {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */ - {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */ - {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */ - /* HSW ULT */ - {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */ - {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */ - {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */ - {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */ - {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */ - {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */ - /* HSW CRW */ - {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */ - {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */ - /* HSW Server */ - {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */ - /* HSW SRVR */ - {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */ - /* BSW */ - {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */ - {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */ - {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */ - {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */ - {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */ - {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */ - {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */ - {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */ - {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */ - {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */ - {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */ -}; - -static void isa_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - dc->desc = "ISA bridge faked to support IGD PT"; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->class_id = PCI_CLASS_BRIDGE_ISA; -}; - -static TypeInfo isa_bridge_info = { - .name = "igd-passthrough-isa-bridge", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PCIDevice), - .class_init = isa_bridge_class_init, -}; - -static void pt_graphics_register_types(void) -{ - type_register_static(&isa_bridge_info); -} -type_init(pt_graphics_register_types) - -void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id) -{ - struct PCIDevice *bridge_dev; - int i, num; - uint16_t pch_dev_id = 0xffff; - uint8_t pch_rev_id; - - num = ARRAY_SIZE(igd_combo_id_infos); - for (i = 0; i < num; i++) { - if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) { - pch_dev_id = igd_combo_id_infos[i].pch_device_id; - pch_rev_id = igd_combo_id_infos[i].pch_revision_id; - } - } - - if (pch_dev_id == 0xffff) { - return; - } - - /* Currently IGD drivers always need to access PCH by 1f.0. */ - bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0), - "igd-passthrough-isa-bridge"); - - /* - * Note that vendor id is always PCI_VENDOR_ID_INTEL. - */ - if (!bridge_dev) { - fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n"); - return; - } - pci_config_set_device_id(bridge_dev->config, pch_dev_id); - pci_config_set_revision(bridge_dev->config, pch_rev_id); -} - static void isapc_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); diff --git a/hw/pci-host/igd.c b/hw/pci-host/igd.c index f6e3f7a..96b679d 100644 --- a/hw/pci-host/igd.c +++ b/hw/pci-host/igd.c @@ -123,10 +123,118 @@ static const TypeInfo igd_passthrough_q35_info = { .class_init = igd_passthrough_q35_class_init, }; +typedef struct { + uint16_t gpu_device_id; + uint16_t pch_device_id; + uint8_t pch_revision_id; +} IGDDeviceIDInfo; + +/* In real world different GPU should have different PCH. But actually + * the different PCH DIDs likely map to different PCH SKUs. We do the + * same thing for the GPU. For PCH, the different SKUs are going to be + * all the same silicon design and implementation, just different + * features turn on and off with fuses. The SW interfaces should be + * consistent across all SKUs in a given family (eg LPT). But just same + * features may not be supported. + * + * Most of these different PCH features probably don't matter to the + * Gfx driver, but obviously any difference in display port connections + * will so it should be fine with any PCH in case of passthrough. + * + * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell) + * scenarios, 0x9cc3 for BDW(Broadwell). + */ +static const IGDDeviceIDInfo igd_combo_id_infos[] = { + /* HSW Classic */ + {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */ + {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */ + {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */ + {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */ + {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */ + /* HSW ULT */ + {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */ + {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */ + {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */ + {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */ + {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */ + {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */ + /* HSW CRW */ + {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */ + {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */ + /* HSW Server */ + {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */ + /* HSW SRVR */ + {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */ + /* BSW */ + {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */ + {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */ + {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */ + {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */ + {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */ + {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */ + {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */ + {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */ + {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */ + {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */ + {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */ +}; + +static void isa_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + dc->desc = "ISA bridge faked to support IGD PT"; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->class_id = PCI_CLASS_BRIDGE_ISA; +}; + +static TypeInfo igd_passthrough_isa_bridge_info = { + .name = "igd-passthrough-isa-bridge", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PCIDevice), + .class_init = isa_bridge_class_init, +}; + +void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id) +{ + struct PCIDevice *bridge_dev; + int i, num; + uint16_t pch_dev_id = 0xffff; + uint8_t pch_rev_id; + + num = ARRAY_SIZE(igd_combo_id_infos); + for (i = 0; i < num; i++) { + if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) { + pch_dev_id = igd_combo_id_infos[i].pch_device_id; + pch_rev_id = igd_combo_id_infos[i].pch_revision_id; + } + } + + if (pch_dev_id == 0xffff) { + return; + } + + /* Currently IGD drivers always need to access PCH by 1f.0. */ + bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0), + "igd-passthrough-isa-bridge"); + + /* + * Note that vendor id is always PCI_VENDOR_ID_INTEL. + */ + if (!bridge_dev) { + fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n"); + return; + } + pci_config_set_device_id(bridge_dev->config, pch_dev_id); + pci_config_set_revision(bridge_dev->config, pch_rev_id); +} + static void igd_register_types(void) { type_register_static(&igd_passthrough_i440fx_info); type_register_static(&igd_passthrough_q35_info); + type_register_static(&igd_passthrough_isa_bridge_info); } type_init(igd_register_types) -- 1.8.3.1
WARNING: multiple messages have this Message-ID (diff)
From: Gerd Hoffmann <kraxel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> To: qemu-devel-qX2TKyscuCcdnm+yROfE0A@public.gmane.org Cc: igvt-g-y27Ovi1pjclAfugRpC6u6w@public.gmane.org, xen-devel-GuqFBffKawuULHF6PoxzQEEOCMrvLtNR@public.gmane.org, Eduardo Habkost <ehabkost-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, Stefano Stabellini <stefano.stabellini-mvvWK6WmYclDPfheJLI6IQ@public.gmane.org>, "Michael S. Tsirkin" <mst-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, Cao jin <caoj.fnst-BthXqXjhjHXQFUHtdCDX3A@public.gmane.org>, vfio-users-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, Paolo Bonzini <pbonzini-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, Richard Henderson <rth-hL46jP5Bxq7R7s880joybQ@public.gmane.org> Subject: [PATCH v3 09/11] igd: move igd-passthrough-isa-bridge to igd.c too Date: Tue, 5 Jan 2016 12:41:36 +0100 [thread overview] Message-ID: <1451994098-6972-10-git-send-email-kraxel@redhat.com> (raw) In-Reply-To: <1451994098-6972-1-git-send-email-kraxel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> Signed-off-by: Gerd Hoffmann <kraxel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> --- hw/i386/pc_piix.c | 113 ------------------------------------------------------ hw/pci-host/igd.c | 108 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+), 113 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6532e32..f36222e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -914,119 +914,6 @@ static void pc_i440fx_0_10_machine_options(MachineClass *m) DEFINE_I440FX_MACHINE(v0_10, "pc-0.10", pc_compat_0_13, pc_i440fx_0_10_machine_options); -typedef struct { - uint16_t gpu_device_id; - uint16_t pch_device_id; - uint8_t pch_revision_id; -} IGDDeviceIDInfo; - -/* In real world different GPU should have different PCH. But actually - * the different PCH DIDs likely map to different PCH SKUs. We do the - * same thing for the GPU. For PCH, the different SKUs are going to be - * all the same silicon design and implementation, just different - * features turn on and off with fuses. The SW interfaces should be - * consistent across all SKUs in a given family (eg LPT). But just same - * features may not be supported. - * - * Most of these different PCH features probably don't matter to the - * Gfx driver, but obviously any difference in display port connections - * will so it should be fine with any PCH in case of passthrough. - * - * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell) - * scenarios, 0x9cc3 for BDW(Broadwell). - */ -static const IGDDeviceIDInfo igd_combo_id_infos[] = { - /* HSW Classic */ - {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */ - {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */ - {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */ - {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */ - {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */ - /* HSW ULT */ - {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */ - {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */ - {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */ - {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */ - {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */ - {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */ - /* HSW CRW */ - {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */ - {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */ - /* HSW Server */ - {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */ - /* HSW SRVR */ - {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */ - /* BSW */ - {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */ - {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */ - {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */ - {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */ - {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */ - {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */ - {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */ - {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */ - {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */ - {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */ - {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */ -}; - -static void isa_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - dc->desc = "ISA bridge faked to support IGD PT"; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->class_id = PCI_CLASS_BRIDGE_ISA; -}; - -static TypeInfo isa_bridge_info = { - .name = "igd-passthrough-isa-bridge", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PCIDevice), - .class_init = isa_bridge_class_init, -}; - -static void pt_graphics_register_types(void) -{ - type_register_static(&isa_bridge_info); -} -type_init(pt_graphics_register_types) - -void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id) -{ - struct PCIDevice *bridge_dev; - int i, num; - uint16_t pch_dev_id = 0xffff; - uint8_t pch_rev_id; - - num = ARRAY_SIZE(igd_combo_id_infos); - for (i = 0; i < num; i++) { - if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) { - pch_dev_id = igd_combo_id_infos[i].pch_device_id; - pch_rev_id = igd_combo_id_infos[i].pch_revision_id; - } - } - - if (pch_dev_id == 0xffff) { - return; - } - - /* Currently IGD drivers always need to access PCH by 1f.0. */ - bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0), - "igd-passthrough-isa-bridge"); - - /* - * Note that vendor id is always PCI_VENDOR_ID_INTEL. - */ - if (!bridge_dev) { - fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n"); - return; - } - pci_config_set_device_id(bridge_dev->config, pch_dev_id); - pci_config_set_revision(bridge_dev->config, pch_rev_id); -} - static void isapc_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); diff --git a/hw/pci-host/igd.c b/hw/pci-host/igd.c index f6e3f7a..96b679d 100644 --- a/hw/pci-host/igd.c +++ b/hw/pci-host/igd.c @@ -123,10 +123,118 @@ static const TypeInfo igd_passthrough_q35_info = { .class_init = igd_passthrough_q35_class_init, }; +typedef struct { + uint16_t gpu_device_id; + uint16_t pch_device_id; + uint8_t pch_revision_id; +} IGDDeviceIDInfo; + +/* In real world different GPU should have different PCH. But actually + * the different PCH DIDs likely map to different PCH SKUs. We do the + * same thing for the GPU. For PCH, the different SKUs are going to be + * all the same silicon design and implementation, just different + * features turn on and off with fuses. The SW interfaces should be + * consistent across all SKUs in a given family (eg LPT). But just same + * features may not be supported. + * + * Most of these different PCH features probably don't matter to the + * Gfx driver, but obviously any difference in display port connections + * will so it should be fine with any PCH in case of passthrough. + * + * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell) + * scenarios, 0x9cc3 for BDW(Broadwell). + */ +static const IGDDeviceIDInfo igd_combo_id_infos[] = { + /* HSW Classic */ + {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */ + {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */ + {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */ + {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */ + {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */ + /* HSW ULT */ + {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */ + {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */ + {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */ + {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */ + {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */ + {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */ + /* HSW CRW */ + {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */ + {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */ + /* HSW Server */ + {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */ + /* HSW SRVR */ + {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */ + /* BSW */ + {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */ + {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */ + {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */ + {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */ + {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */ + {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */ + {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */ + {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */ + {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */ + {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */ + {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */ +}; + +static void isa_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + dc->desc = "ISA bridge faked to support IGD PT"; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->class_id = PCI_CLASS_BRIDGE_ISA; +}; + +static TypeInfo igd_passthrough_isa_bridge_info = { + .name = "igd-passthrough-isa-bridge", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PCIDevice), + .class_init = isa_bridge_class_init, +}; + +void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id) +{ + struct PCIDevice *bridge_dev; + int i, num; + uint16_t pch_dev_id = 0xffff; + uint8_t pch_rev_id; + + num = ARRAY_SIZE(igd_combo_id_infos); + for (i = 0; i < num; i++) { + if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) { + pch_dev_id = igd_combo_id_infos[i].pch_device_id; + pch_rev_id = igd_combo_id_infos[i].pch_revision_id; + } + } + + if (pch_dev_id == 0xffff) { + return; + } + + /* Currently IGD drivers always need to access PCH by 1f.0. */ + bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0), + "igd-passthrough-isa-bridge"); + + /* + * Note that vendor id is always PCI_VENDOR_ID_INTEL. + */ + if (!bridge_dev) { + fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n"); + return; + } + pci_config_set_device_id(bridge_dev->config, pch_dev_id); + pci_config_set_revision(bridge_dev->config, pch_rev_id); +} + static void igd_register_types(void) { type_register_static(&igd_passthrough_i440fx_info); type_register_static(&igd_passthrough_q35_info); + type_register_static(&igd_passthrough_isa_bridge_info); } type_init(igd_register_types) -- 1.8.3.1
next prev parent reply other threads:[~2016-01-05 11:42 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-05 11:41 [Qemu-devel] [PATCH v3 00/11] igd passthrough chipset tweaks Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 01/11] pc: wire up TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE for !xen Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 02/11] pc: remove has_igd_gfx_passthru global Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 14:32 ` [Qemu-devel] [Xen-devel] " Stefano Stabellini 2016-01-06 14:32 ` Stefano Stabellini 2016-01-19 15:09 ` [Qemu-devel] " Eduardo Habkost 2016-01-19 15:09 ` Eduardo Habkost 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 03/11] pc: move igd support code to igd.c Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 04/11] igd: switch TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE to realize Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 14:32 ` [Qemu-devel] " Stefano Stabellini 2016-01-06 14:32 ` Stefano Stabellini 2016-01-23 14:51 ` [Qemu-devel] " Eduardo Habkost 2016-01-23 14:51 ` Eduardo Habkost 2016-01-25 8:59 ` [Qemu-devel] " Gerd Hoffmann 2016-01-25 8:59 ` Gerd Hoffmann 2016-01-25 11:53 ` [Qemu-devel] " Stefano Stabellini 2016-01-25 11:53 ` Stefano Stabellini 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 05/11] igd: TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE: call parent realize Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 14:41 ` [Qemu-devel] " Stefano Stabellini 2016-01-06 14:41 ` Stefano Stabellini 2016-01-06 15:45 ` [Qemu-devel] " Gerd Hoffmann 2016-01-06 15:45 ` Gerd Hoffmann 2016-01-19 15:13 ` [Qemu-devel] " Eduardo Habkost 2016-01-19 15:13 ` Eduardo Habkost 2016-01-20 9:10 ` [Qemu-devel] " Gerd Hoffmann 2016-01-20 9:10 ` Gerd Hoffmann 2016-01-23 14:52 ` [Qemu-devel] " Eduardo Habkost 2016-01-23 14:52 ` Eduardo Habkost 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 06/11] igd: use defines for standard pci config space offsets Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 14:43 ` [Qemu-devel] " Stefano Stabellini 2016-01-06 14:43 ` Stefano Stabellini 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 07/11] igd: revamp host config read Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 15:02 ` [Qemu-devel] " Stefano Stabellini 2016-01-06 15:02 ` Stefano Stabellini 2016-01-06 15:51 ` [Qemu-devel] " Gerd Hoffmann 2016-01-06 15:51 ` Gerd Hoffmann 2016-01-06 16:23 ` [Qemu-devel] [Xen-devel] " Stefano Stabellini 2016-01-06 16:23 ` Stefano Stabellini 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 08/11] igd: add q35 support Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann [this message] 2016-01-05 11:41 ` [PATCH v3 09/11] igd: move igd-passthrough-isa-bridge to igd.c too Gerd Hoffmann 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 10/11] igd: handle igd-passthrough-isa-bridge setup in realize() Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 15:29 ` [Qemu-devel] " Stefano Stabellini 2016-01-06 15:29 ` Stefano Stabellini 2016-01-06 15:52 ` [Qemu-devel] " Gerd Hoffmann 2016-01-06 15:52 ` Gerd Hoffmann 2016-01-05 11:41 ` [Qemu-devel] [PATCH v3 11/11] igd: move igd-passthrough-isa-bridge creation to machine init Gerd Hoffmann 2016-01-05 11:41 ` Gerd Hoffmann 2016-01-06 15:36 ` [Qemu-devel] " Stefano Stabellini 2016-01-06 15:36 ` Stefano Stabellini 2016-01-07 7:38 ` [Qemu-devel] " Gerd Hoffmann 2016-01-07 7:38 ` Gerd Hoffmann 2016-01-07 13:10 ` [Qemu-devel] " Stefano Stabellini 2016-01-07 13:10 ` Stefano Stabellini 2016-01-07 15:50 ` [Qemu-devel] " Gerd Hoffmann 2016-01-07 15:50 ` Gerd Hoffmann 2016-01-08 11:20 ` Stefano Stabellini 2016-01-08 11:20 ` Stefano Stabellini 2016-01-08 12:12 ` [Qemu-devel] " Stefano Stabellini 2016-01-08 12:12 ` Stefano Stabellini 2016-01-08 12:32 ` Gerd Hoffmann 2016-01-08 12:32 ` Gerd Hoffmann 2016-01-08 12:38 ` [Qemu-devel] " Stefano Stabellini 2016-01-08 12:38 ` Stefano Stabellini 2016-01-05 13:07 ` [Qemu-devel] [PATCH v3 00/11] igd passthrough chipset tweaks Michael S. Tsirkin 2016-01-05 13:07 ` Michael S. Tsirkin 2016-01-28 19:35 ` [Qemu-devel] [vfio-users] " Alex Williamson 2016-01-28 19:35 ` Alex Williamson 2016-01-29 2:22 ` [Qemu-devel] [iGVT-g] " Kay, Allen M 2016-01-29 2:22 ` Kay, Allen M 2016-01-29 2:54 ` [Qemu-devel] " Alex Williamson 2016-01-29 2:54 ` Alex Williamson 2016-01-29 6:21 ` [Qemu-devel] " Jike Song 2016-01-29 6:21 ` Jike Song 2016-01-29 21:58 ` [Qemu-devel] " Kay, Allen M 2016-01-29 21:58 ` Kay, Allen M 2016-02-02 7:07 ` [Qemu-devel] " Tian, Kevin 2016-02-02 7:07 ` Tian, Kevin 2016-02-02 19:10 ` [Qemu-devel] " Kay, Allen M 2016-02-02 19:10 ` [iGVT-g] " Kay, Allen M 2016-02-02 19:37 ` [Qemu-devel] [iGVT-g] [vfio-users] " Alex Williamson 2016-02-02 19:37 ` Alex Williamson 2016-02-02 23:32 ` [Qemu-devel] " Kay, Allen M 2016-02-02 23:32 ` Kay, Allen M 2016-01-29 7:09 ` [Qemu-devel] " Gerd Hoffmann 2016-01-29 7:09 ` Gerd Hoffmann 2016-01-29 17:59 ` [Qemu-devel] " Alex Williamson 2016-01-29 17:59 ` Alex Williamson 2016-01-30 1:18 ` [Qemu-devel] [iGVT-g] " Kay, Allen M 2016-01-30 1:18 ` Kay, Allen M 2016-01-31 17:42 ` [Qemu-devel] " Alex Williamson 2016-01-31 17:42 ` Alex Williamson 2016-02-02 0:04 ` [Qemu-devel] " Kay, Allen M 2016-02-02 0:04 ` Kay, Allen M 2016-02-02 6:42 ` [Qemu-devel] [Xen-devel] " Tian, Kevin 2016-02-02 6:42 ` Tian, Kevin 2016-02-02 11:50 ` [Qemu-devel] " David Woodhouse 2016-02-02 11:50 ` David Woodhouse 2016-02-02 14:54 ` [Qemu-devel] " Alex Williamson 2016-02-02 14:54 ` Alex Williamson 2016-02-02 15:06 ` [Qemu-devel] " David Woodhouse 2016-02-02 15:06 ` David Woodhouse 2016-02-02 14:38 ` [Qemu-devel] " Alex Williamson 2016-02-02 14:38 ` Alex Williamson 2016-02-01 12:49 ` [Qemu-devel] " Gerd Hoffmann 2016-02-01 12:49 ` Gerd Hoffmann 2016-02-01 22:16 ` [Qemu-devel] " Alex Williamson 2016-02-01 22:16 ` Alex Williamson 2016-02-02 7:43 ` [Qemu-devel] [vfio-users] " Gerd Hoffmann 2016-02-02 7:43 ` Gerd Hoffmann 2016-02-02 7:01 ` [Qemu-devel] [iGVT-g] " Tian, Kevin 2016-02-02 7:01 ` [iGVT-g] " Tian, Kevin 2016-02-02 8:56 ` [Qemu-devel] [iGVT-g] [vfio-users] " Gerd Hoffmann 2016-02-02 8:56 ` Gerd Hoffmann 2016-02-02 16:31 ` [Qemu-devel] " Kevin O'Connor 2016-02-02 16:31 ` Kevin O'Connor 2016-02-02 16:49 ` [Qemu-devel] " Laszlo Ersek 2016-02-02 16:49 ` Laszlo Ersek 2016-02-02 20:18 ` [Qemu-devel] " Alex Williamson 2016-02-02 20:18 ` Alex Williamson 2016-02-03 6:08 ` [Qemu-devel] " Tian, Kevin 2016-02-03 6:08 ` Tian, Kevin
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