From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
Mika Kuoppala <mika.kuoppala@intel.com>
Subject: [PATCH v2 1/6] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+
Date: Sat, 16 Jan 2016 09:46:15 +0000 [thread overview]
Message-ID: <1452937580-3625-1-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1452868545-19586-1-git-send-email-chris@chris-wilson.co.uk>
In order to ensure seqno/irq coherency, we currently read a ring register.
The mmio transaction following the interrupt delays the inspection of
the seqno long enough for the MI_STORE_DWORD_IMM to update the CPU
cache. However, it is only the memory timing that is important for the
purposes of the delay, we do not need nor desire the extra forcewake.
v3: Update commentary
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [v2]
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8cd8aabcc3ff..ddfe511ee9ba 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1492,10 +1492,19 @@ gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
{
/* Workaround to force correct ordering between irq and seqno writes on
* ivb (and maybe also on snb) by reading from a CS register (like
- * ACTHD) before reading the status page. */
+ * ACTHD) before reading the status page.
+ *
+ * Note that this effectively stalls the read by the time it takes to
+ * do a memory transaction, which more or less ensures that the write
+ * from the GPU has sufficient time to invalidate the CPU cacheline.
+ * Alternatively we could delay the interrupt from the CS ring to give
+ * the write time to land, but that would incur a delay after every
+ * batch i.e. much more frequent than a delay when waiting for the
+ * interrupt (with the same net latency).
+ */
if (!lazy_coherency) {
struct drm_i915_private *dev_priv = ring->dev->dev_private;
- POSTING_READ(RING_ACTHD(ring->mmio_base));
+ POSTING_READ_FW(RING_ACTHD(ring->mmio_base));
}
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
--
2.7.0.rc3
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next prev parent reply other threads:[~2016-01-16 9:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-15 14:35 "missed-interrupt" syndrome on Broadwell+ Chris Wilson
2016-01-15 14:35 ` [PATCH 1/6] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ Chris Wilson
2016-01-15 17:55 ` Mika Kuoppala
2016-01-15 14:35 ` [PATCH 2/6] drm/i915: Separate out the seqno-barrier from engine->get_seqno Chris Wilson
2016-01-15 14:35 ` [PATCH 3/6] drm/i915: Broadwell execlists needs exactly the same seqno w/a as legacy Chris Wilson
2016-01-15 14:35 ` [PATCH 4/6] drm/i915: Harden detection of missed interrupts Chris Wilson
2016-01-15 14:35 ` [PATCH 5/6] drm/i915: Use simplest form for flushing the single cacheline in the HWS Chris Wilson
2016-01-15 14:35 ` [PATCH 6/6] drm/i915: Replace manual barrier() with READ_ONCE() in HWS accessor Chris Wilson
2016-01-15 15:20 ` ✗ Fi.CI.BAT: warning for series starting with [1/6] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ Patchwork
2016-01-16 9:46 ` Chris Wilson [this message]
2016-01-16 9:46 ` [PATCH v2 2/6] drm/i915: Separate out the seqno-barrier from engine->get_seqno Chris Wilson
2016-01-16 9:46 ` [PATCH v2 3/6] drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists Chris Wilson
2016-01-18 8:58 ` [PATCH] magic-clflush-fix Chris Wilson
2016-01-18 9:02 ` Chris Wilson
2016-01-18 9:02 ` [PATCH] drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists Chris Wilson
2016-01-16 9:46 ` [PATCH v2 4/6] drm/i915: Harden detection of missed interrupts Chris Wilson
2016-01-18 13:07 ` Mika Kuoppala
2016-01-18 15:35 ` Chris Wilson
2016-01-16 9:46 ` [PATCH v2 5/6] drm/i915: Use simplest form for flushing the single cacheline in the HWS Chris Wilson
2016-01-16 9:46 ` [PATCH v2 6/6] drm/i915: Replace manual barrier() with READ_ONCE() in HWS accessor Chris Wilson
2016-01-16 10:01 ` ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ (rev6) Patchwork
2016-01-18 9:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ (rev8) Patchwork
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