[PATCH v2 5/6] drm/i915: Use simplest form for flushing the single cacheline in the HWS

From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Subject: [PATCH v2 5/6] drm/i915: Use simplest form for flushing the single cacheline in the HWS
Date: Sat, 16 Jan 2016 09:46:19 +0000	[thread overview]
Message-ID: <1452937580-3625-5-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1452937580-3625-1-git-send-email-chris@chris-wilson.co.uk>

Rather than call a function to compute the matching cachelines and
clflush them, just call the clflush *instruction* directly. We also know
that we can use the unpatched plain clflush rather than the clflushopt
alternative.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b30ad99a54bf..cdd9ac88b055 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -389,8 +389,9 @@ intel_ring_sync_index(struct intel_engine_cs *ring,
 static inline void
 intel_flush_status_page(struct intel_engine_cs *ring, int reg)
 {
-	drm_clflush_virt_range(&ring->status_page.page_addr[reg],
-			       sizeof(uint32_t));
+	mb();
+	clflush(&ring->status_page.page_addr[reg]);
+	mb();
 }
 
 static inline u32
-- 
2.7.0.rc3

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