From: Chen-Yu Tsai <wens@csie.org> To: Ulf Hansson <ulf.hansson@linaro.org>, Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org>, Hans de Goede <hdegoede@redhat.com>, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Date: Thu, 21 Jan 2016 13:26:35 +0800 [thread overview] Message-ID: <1453354002-28366-9-git-send-email-wens@csie.org> (raw) In-Reply-To: <1453354002-28366-1-git-send-email-wens@csie.org> mmc2 and mmc3 are available on the same pins, with different mux values. However, only mmc3 supports 8 bit DDR transfer modes. Since preference for mmc3 over mmc2 is due to DDR transfer modes, just set the drive strength to 40mA, which is needed for DDR. This pinmux setting also includes the hardware reset pin for emmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b6ad7850fac6..1867af24ff52 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -709,6 +709,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc3_8bit_emmc_pins: mmc3@1 { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC24"; + allwinner,function = "mmc3"; + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + gmac_pins_mii_a: gmac_mii@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA8", "PA9", "PA11", -- 2.7.0.rc3
WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Date: Thu, 21 Jan 2016 13:26:35 +0800 [thread overview] Message-ID: <1453354002-28366-9-git-send-email-wens@csie.org> (raw) In-Reply-To: <1453354002-28366-1-git-send-email-wens@csie.org> mmc2 and mmc3 are available on the same pins, with different mux values. However, only mmc3 supports 8 bit DDR transfer modes. Since preference for mmc3 over mmc2 is due to DDR transfer modes, just set the drive strength to 40mA, which is needed for DDR. This pinmux setting also includes the hardware reset pin for emmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b6ad7850fac6..1867af24ff52 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -709,6 +709,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc3_8bit_emmc_pins: mmc3 at 1 { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC24"; + allwinner,function = "mmc3"; + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + gmac_pins_mii_a: gmac_mii at 0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA8", "PA9", "PA11", -- 2.7.0.rc3
next prev parent reply other threads:[~2016-01-21 5:35 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-21 5:26 [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 5:26 ` [PATCH RFC 01/15] mmc: sunxi: Document host init sequence Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-29 11:39 ` Ulf Hansson 2016-01-29 11:39 ` Ulf Hansson 2016-01-29 11:39 ` Ulf Hansson 2016-01-21 5:26 ` [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-29 11:40 ` Ulf Hansson 2016-01-29 11:40 ` Ulf Hansson 2016-01-29 11:40 ` Ulf Hansson 2016-01-21 5:26 ` [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11) Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-29 10:42 ` Ulf Hansson 2016-01-29 10:42 ` Ulf Hansson 2016-01-29 10:42 ` Ulf Hansson 2016-01-29 14:44 ` Chen-Yu Tsai 2016-01-29 14:44 ` Chen-Yu Tsai 2016-01-29 14:44 ` Chen-Yu Tsai 2016-01-21 5:26 ` [PATCH RFC 04/15] mmc: sunxi: Support vqmmc regulator Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-29 11:40 ` Ulf Hansson 2016-01-29 11:40 ` Ulf Hansson 2016-01-29 11:40 ` Ulf Hansson 2016-01-21 5:26 ` [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 11:14 ` Hans de Goede 2016-01-21 11:14 ` Hans de Goede 2016-01-21 11:55 ` Chen-Yu Tsai 2016-01-21 11:55 ` Chen-Yu Tsai 2016-01-21 12:26 ` Hans de Goede 2016-01-21 12:26 ` Hans de Goede 2016-01-21 12:26 ` Hans de Goede 2016-01-21 5:26 ` [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 5:26 ` [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai [this message] 2016-01-21 5:26 ` [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai 2016-01-22 20:31 ` Maxime Ripard 2016-01-22 20:31 ` Maxime Ripard 2016-01-22 20:31 ` Maxime Ripard 2016-01-23 11:04 ` Chen-Yu Tsai 2016-01-23 11:04 ` Chen-Yu Tsai 2016-01-23 11:04 ` Chen-Yu Tsai 2016-01-24 16:54 ` Maxime Ripard 2016-01-24 16:54 ` Maxime Ripard 2016-01-24 16:54 ` Maxime Ripard 2016-01-21 5:26 ` [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 11:16 ` Hans de Goede 2016-01-21 11:16 ` Hans de Goede 2016-01-21 11:16 ` Hans de Goede 2016-01-21 12:23 ` Chen-Yu Tsai 2016-01-21 12:23 ` Chen-Yu Tsai 2016-01-21 12:25 ` Hans de Goede 2016-01-21 12:25 ` Hans de Goede 2016-01-21 12:28 ` Chen-Yu Tsai 2016-01-21 12:28 ` Chen-Yu Tsai 2016-01-21 12:38 ` Hans de Goede 2016-01-21 12:38 ` Hans de Goede 2016-01-22 20:39 ` Maxime Ripard 2016-01-22 20:39 ` Maxime Ripard 2016-01-22 20:39 ` Maxime Ripard 2016-01-23 4:21 ` Chen-Yu Tsai 2016-01-23 4:21 ` Chen-Yu Tsai 2016-01-23 4:21 ` Chen-Yu Tsai 2016-01-24 16:56 ` Maxime Ripard 2016-01-24 16:56 ` Maxime Ripard 2016-01-24 16:56 ` Maxime Ripard 2016-01-21 5:26 ` [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-24 16:58 ` Maxime Ripard 2016-01-24 16:58 ` Maxime Ripard 2016-01-24 16:58 ` Maxime Ripard 2016-01-21 5:26 ` [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-22 20:42 ` Maxime Ripard 2016-01-22 20:42 ` Maxime Ripard 2016-01-22 20:42 ` Maxime Ripard 2016-01-21 5:26 ` [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-22 20:44 ` Maxime Ripard 2016-01-22 20:44 ` Maxime Ripard 2016-01-22 20:44 ` Maxime Ripard 2016-01-23 10:50 ` Chen-Yu Tsai 2016-01-23 10:50 ` Chen-Yu Tsai 2016-01-23 10:50 ` Chen-Yu Tsai 2016-01-21 5:26 ` [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-24 16:58 ` Maxime Ripard 2016-01-24 16:58 ` Maxime Ripard 2016-01-24 16:58 ` Maxime Ripard 2016-01-21 5:26 ` [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-24 16:59 ` Maxime Ripard 2016-01-24 16:59 ` Maxime Ripard 2016-01-21 5:26 ` [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: " Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-21 5:26 ` Chen-Yu Tsai 2016-01-24 16:59 ` Maxime Ripard 2016-01-24 16:59 ` Maxime Ripard 2016-01-21 11:19 ` [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Hans de Goede 2016-01-21 11:19 ` Hans de Goede 2016-01-21 11:19 ` Hans de Goede
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