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From: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
To: Nishanth Menon <nm@ti.com>,
	Eduardo Valentin <edubezval@gmail.com>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>
Cc: Kevin Hilman <khilman@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: [RFC PATCH 3/5] dt-bindings: thermal: Add optional properties of Mediatek thermal controller
Date: Fri, 22 Jan 2016 16:40:27 +0800	[thread overview]
Message-ID: <1453452029-20843-4-git-send-email-pi-cheng.chen@linaro.org> (raw)
In-Reply-To: <1453452029-20843-1-git-send-email-pi-cheng.chen@linaro.org>

This adds optional properties of Mediatek thermal controller which are
required by SVS engine integrated with Mediatek thermal controller.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
---
 .../bindings/thermal/mediatek-thermal.txt          | 23 ++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
index 81f9a51..acaacaa 100644
--- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
@@ -7,6 +7,11 @@ this device needs phandles to the AUXADC. Also it controls a mux in the
 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
 is also needed.
 
+There is another hardware engine, SVS (Smart Voltage Scaling) which shares the
+same block of banked registers with Mediatek thermal controller. Hence the
+driver of SVS is integrated with the driver of Mediatek thermal controller. The
+properties required by SVS engine are optional for Mediatek thermal controller.
+
 Required properties:
 - compatible: "mediatek,mt8173-thermal"
 - reg: Address range of the thermal controller
@@ -21,9 +26,15 @@ Required properties:
 - #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description.
 
 Optional properties:
-- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
-               unspecified default values shall be used.
-- nvmem-cell-names: Should be "calibration-data"
+- clocks, clock-names: Clocks that are optional for the thermal controller.
+	       Specify to enable SVS engine.
+	       "svs_pll": The PLL clock should be switched to during
+			  initialization stage of SVS engine.
+	       "svs_mux": The MUX clock controls the clock input of SVS engine.
+- nvmem-cells: A list of phandles to the calibration data provided by a nvmem
+	       device. If unspecified default values shall be used. The SVS
+	       engine will be disabled if no SVS calibration data is specified.
+- nvmem-cell-names: Should be "calibration-data" and "svs-calibration-data"
 
 Example:
 
@@ -33,11 +44,11 @@ Example:
 		reg = <0 0x1100b000 0 0x1000>;
 		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
-		clock-names = "therm", "auxadc";
+		clock-names = "therm", "auxadc", ;
 		resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 		reset-names = "therm";
 		mediatek,auxadc = <&auxadc>;
 		mediatek,apmixedsys = <&apmixedsys>;
-		nvmem-cells = <&thermal_calibration_data>;
-		nvmem-cell-names = "calibration-data";
+		nvmem-cells = <&thermal_calibration_data>, <&svs-calibration>;
+		nvmem-cell-names = "calibration-data", "svs-calibration-data";
 	};
-- 
1.9.1


WARNING: multiple messages have this Message-ID (diff)
From: pi-cheng.chen@linaro.org (Pi-Cheng Chen)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 3/5] dt-bindings: thermal: Add optional properties of Mediatek thermal controller
Date: Fri, 22 Jan 2016 16:40:27 +0800	[thread overview]
Message-ID: <1453452029-20843-4-git-send-email-pi-cheng.chen@linaro.org> (raw)
In-Reply-To: <1453452029-20843-1-git-send-email-pi-cheng.chen@linaro.org>

This adds optional properties of Mediatek thermal controller which are
required by SVS engine integrated with Mediatek thermal controller.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
---
 .../bindings/thermal/mediatek-thermal.txt          | 23 ++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
index 81f9a51..acaacaa 100644
--- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
@@ -7,6 +7,11 @@ this device needs phandles to the AUXADC. Also it controls a mux in the
 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
 is also needed.
 
+There is another hardware engine, SVS (Smart Voltage Scaling) which shares the
+same block of banked registers with Mediatek thermal controller. Hence the
+driver of SVS is integrated with the driver of Mediatek thermal controller. The
+properties required by SVS engine are optional for Mediatek thermal controller.
+
 Required properties:
 - compatible: "mediatek,mt8173-thermal"
 - reg: Address range of the thermal controller
@@ -21,9 +26,15 @@ Required properties:
 - #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description.
 
 Optional properties:
-- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
-               unspecified default values shall be used.
-- nvmem-cell-names: Should be "calibration-data"
+- clocks, clock-names: Clocks that are optional for the thermal controller.
+	       Specify to enable SVS engine.
+	       "svs_pll": The PLL clock should be switched to during
+			  initialization stage of SVS engine.
+	       "svs_mux": The MUX clock controls the clock input of SVS engine.
+- nvmem-cells: A list of phandles to the calibration data provided by a nvmem
+	       device. If unspecified default values shall be used. The SVS
+	       engine will be disabled if no SVS calibration data is specified.
+- nvmem-cell-names: Should be "calibration-data" and "svs-calibration-data"
 
 Example:
 
@@ -33,11 +44,11 @@ Example:
 		reg = <0 0x1100b000 0 0x1000>;
 		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
-		clock-names = "therm", "auxadc";
+		clock-names = "therm", "auxadc", ;
 		resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 		reset-names = "therm";
 		mediatek,auxadc = <&auxadc>;
 		mediatek,apmixedsys = <&apmixedsys>;
-		nvmem-cells = <&thermal_calibration_data>;
-		nvmem-cell-names = "calibration-data";
+		nvmem-cells = <&thermal_calibration_data>, <&svs-calibration>;
+		nvmem-cell-names = "calibration-data", "svs-calibration-data";
 	};
-- 
1.9.1

  parent reply	other threads:[~2016-01-22  8:40 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-22  8:40 [RFC PATCH 0/5] Add support for Mediatek SVS engine Pi-Cheng Chen
2016-01-22  8:40 ` Pi-Cheng Chen
2016-01-22  8:40 ` [RFC PATCH 1/5] thermal: MT8173: Replace mutex with spinlock Pi-Cheng Chen
2016-01-22  8:40   ` Pi-Cheng Chen
2016-01-22  8:40 ` [RFC PATCH 2/5] cpufreq: mt8173: Remove platform device registration code Pi-Cheng Chen
2016-01-22  8:40   ` Pi-Cheng Chen
2016-01-22  8:40 ` Pi-Cheng Chen [this message]
2016-01-22  8:40   ` [RFC PATCH 3/5] dt-bindings: thermal: Add optional properties of Mediatek thermal controller Pi-Cheng Chen
2016-01-22 22:31   ` Rob Herring
2016-01-22 22:31     ` Rob Herring
2016-01-25  0:21     ` Pi-Cheng Chen
2016-01-25  0:21       ` Pi-Cheng Chen
2016-01-22  8:40 ` [RFC PATCH 4/5] PM / AVS: thermal: MT8173: Introduce support for SVS engine Pi-Cheng Chen
2016-01-22  8:40   ` Pi-Cheng Chen
2016-01-22 23:38   ` Daniel Kurtz
2016-01-22 23:38     ` Daniel Kurtz
2016-02-18  3:00     ` Pi-Cheng Chen
2016-02-18  3:00       ` Pi-Cheng Chen
2016-02-19  5:08       ` Henry Chen
2016-02-19  5:08         ` Henry Chen
2016-02-19  5:31         ` Henry Chen
2016-02-19  5:31           ` Henry Chen
2016-01-22  8:40 ` [PATCH 5/5] cpufreq: mt8173: Add notifier to handle OPP voltage adjustment Pi-Cheng Chen
2016-01-22  8:40   ` Pi-Cheng Chen

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