From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>, <marc.zyngier@arm.com>,
<christoffer.dall@linaro.org>
Cc: <linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
<will.deacon@arm.com>, <wei@redhat.com>, <cov@codeaurora.org>,
<shannon.zhao@linaro.org>, <peter.huangpeng@huawei.com>,
<hangaohuai@huawei.com>, <zhaoshenglong@huawei.com>
Subject: [PATCH v12 14/21] KVM: ARM64: Add helper to handle PMCR register bits
Date: Mon, 22 Feb 2016 17:37:50 +0800 [thread overview]
Message-ID: <1456133877-9584-15-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1456133877-9584-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kvm/sys_regs.c | 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 37 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f31023b..f1866c3 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -467,6 +467,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
val &= ~ARMV8_PMU_PMCR_MASK;
val |= p->regval & ARMV8_PMU_PMCR_MASK;
vcpu_sys_reg(vcpu, PMCR_EL0) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
} else {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, PMCR_EL0)
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 348c4c9..8bc92d1 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -45,6 +45,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -67,6 +68,7 @@ static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
+static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data, u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 9fc775e..cda869c 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -210,6 +210,40 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
}
}
+/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
+{
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+ u64 mask;
+ int i;
+
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ if (val & ARMV8_PMU_PMCR_E) {
+ kvm_pmu_enable_counter(vcpu,
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);
+ } else {
+ kvm_pmu_disable_counter(vcpu, mask);
+ }
+
+ if (val & ARMV8_PMU_PMCR_C)
+ kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
+
+ if (val & ARMV8_PMU_PMCR_P) {
+ for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++)
+ kvm_pmu_set_counter_value(vcpu, i, 0);
+ }
+
+ if (val & ARMV8_PMU_PMCR_LC) {
+ pmc = &pmu->pmc[ARMV8_PMU_CYCLE_IDX];
+ pmc->bitmask = 0xffffffffffffffffUL;
+ }
+}
+
static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
{
return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) &&
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com,
christoffer.dall@linaro.org
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
will.deacon@arm.com, wei@redhat.com, cov@codeaurora.org,
shannon.zhao@linaro.org, peter.huangpeng@huawei.com,
hangaohuai@huawei.com, zhaoshenglong@huawei.com
Subject: [PATCH v12 14/21] KVM: ARM64: Add helper to handle PMCR register bits
Date: Mon, 22 Feb 2016 17:37:50 +0800 [thread overview]
Message-ID: <1456133877-9584-15-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1456133877-9584-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kvm/sys_regs.c | 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 37 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f31023b..f1866c3 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -467,6 +467,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
val &= ~ARMV8_PMU_PMCR_MASK;
val |= p->regval & ARMV8_PMU_PMCR_MASK;
vcpu_sys_reg(vcpu, PMCR_EL0) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
} else {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, PMCR_EL0)
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 348c4c9..8bc92d1 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -45,6 +45,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -67,6 +68,7 @@ static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
+static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data, u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 9fc775e..cda869c 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -210,6 +210,40 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
}
}
+/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
+{
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+ u64 mask;
+ int i;
+
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ if (val & ARMV8_PMU_PMCR_E) {
+ kvm_pmu_enable_counter(vcpu,
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);
+ } else {
+ kvm_pmu_disable_counter(vcpu, mask);
+ }
+
+ if (val & ARMV8_PMU_PMCR_C)
+ kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
+
+ if (val & ARMV8_PMU_PMCR_P) {
+ for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++)
+ kvm_pmu_set_counter_value(vcpu, i, 0);
+ }
+
+ if (val & ARMV8_PMU_PMCR_LC) {
+ pmc = &pmu->pmc[ARMV8_PMU_CYCLE_IDX];
+ pmc->bitmask = 0xffffffffffffffffUL;
+ }
+}
+
static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
{
return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) &&
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v12 14/21] KVM: ARM64: Add helper to handle PMCR register bits
Date: Mon, 22 Feb 2016 17:37:50 +0800 [thread overview]
Message-ID: <1456133877-9584-15-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1456133877-9584-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kvm/sys_regs.c | 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 37 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f31023b..f1866c3 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -467,6 +467,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
val &= ~ARMV8_PMU_PMCR_MASK;
val |= p->regval & ARMV8_PMU_PMCR_MASK;
vcpu_sys_reg(vcpu, PMCR_EL0) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
} else {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, PMCR_EL0)
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 348c4c9..8bc92d1 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -45,6 +45,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -67,6 +68,7 @@ static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
+static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data, u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 9fc775e..cda869c 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -210,6 +210,40 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
}
}
+/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
+{
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+ u64 mask;
+ int i;
+
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ if (val & ARMV8_PMU_PMCR_E) {
+ kvm_pmu_enable_counter(vcpu,
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);
+ } else {
+ kvm_pmu_disable_counter(vcpu, mask);
+ }
+
+ if (val & ARMV8_PMU_PMCR_C)
+ kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
+
+ if (val & ARMV8_PMU_PMCR_P) {
+ for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++)
+ kvm_pmu_set_counter_value(vcpu, i, 0);
+ }
+
+ if (val & ARMV8_PMU_PMCR_LC) {
+ pmc = &pmu->pmc[ARMV8_PMU_CYCLE_IDX];
+ pmc->bitmask = 0xffffffffffffffffUL;
+ }
+}
+
static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
{
return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) &&
--
2.0.4
next prev parent reply other threads:[~2016-02-22 9:39 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-22 9:37 [PATCH v12 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 01/21] ARM64: Move PMU register related defines to asm/perf_event.h Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 17:51 ` Marc Zyngier
2016-02-22 17:51 ` Marc Zyngier
2016-02-23 1:46 ` Shannon Zhao
2016-02-23 1:46 ` Shannon Zhao
2016-02-23 1:46 ` Shannon Zhao
2016-02-23 8:33 ` Marc Zyngier
2016-02-23 8:33 ` Marc Zyngier
2016-02-23 9:29 ` Shannon Zhao
2016-02-23 9:29 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-23 17:42 ` Marc Zyngier
2016-02-23 17:42 ` Marc Zyngier
2016-02-24 1:27 ` Shannon Zhao
2016-02-24 1:27 ` Shannon Zhao
2016-02-24 1:27 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao [this message]
2016-02-22 9:37 ` [PATCH v12 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-23 14:14 ` Marc Zyngier
2016-02-23 14:14 ` Marc Zyngier
2016-02-23 14:52 ` Shannon Zhao
2016-02-23 14:52 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
2016-02-22 9:37 ` Shannon Zhao
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